Wait Timer For Flow Control Registers; Chip Select Override Registers - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: SPI0/SPI1

WAIT TIMER FOR FLOW CONTROL REGISTERS

Address: 0x4000402C, Reset: 0x0000, Name: SPI0_WAIT_TMR
Address: 0x4002402C, Reset: 0x0000, Name: SPI1_WAIT_TMR
This register is only used in initiator mode.
Table 317. Bit Descriptions for SPI0_WAIT_TMR, SPI1_WAIT_TMR
Bits Bit Name Settings
[15:0] VALUE

CHIP SELECT OVERRIDE REGISTERS

Address: 0x40004034, Reset: 0x0000, Name: SPI0_CS_OVERRIDE
Address: 0x40024034, Reset: 0x0000, Name: SPI1_CS_OVERRIDE
This register is only used in initiator mode.
Table 318. Bit Descriptions for CS_OVERRIDE
Bits Bit Name Settings
[15:2] Reserved
[1:0] CTL
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Description
Wait Timer for Flow Control. This field specifies the number of SCLK cycles to wait before continuing the
SPI read. This field can take values of 0 to 65,535. This field is only valid if SPIx_FLOW_CTL, Bits[1:0] =
0b01b. For all other values of SPIx_FLOW_CTL, Bits[1:0], this field is ignored. A value of 0 implies a wait
time of 1 SCLK cycle.
Description
Reserved.
Chip Select Override Control. This bit overrides the chip select output from the initiator state machine. This bit
may be needed for special SPI transfers. Do not use for normal SPI transfers.
00 Chip select is not forced.
01 Chip select is forced to drive 1.
10 Chip select is forced to drive 0.
11 Chip select is not forced.
ADuCM356
Reset Access
0x0000 R/W
Reset Access
0x0 R
0x0 R/W
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