Register Details: System Resets; Digital Die Reset Status Register; Always On Reset Status Register; Analog Die Status Register - Analog Devices ADuCM356 Reference Manual

Reference Manual

REGISTER DETAILS: SYSTEM RESETS

DIGITAL DIE RESET STATUS REGISTER

Address: 0x4004C040, Reset: 0x000000XX, Name: RST_STAT
Table 37. Bit Descriptions for RST_STAT
Bits Bit Name Settings
[15:6] Reserved
[5:4] PORSRC
3 SWRST
2 Reserved
1 EXTRST
0 POR

ALWAYS ON RESET STATUS REGISTER

Address: 0x400C0A40, Reset: 0x000X, Name: RSTSTA
Table 38. Bit Descriptions for RSTSTA
Bits Bit Name Settings
[15:3] Reserved
2 WDRST
1 EXTRST
0 POR

ANALOG DIE STATUS REGISTER

Address: 0x40007008, Reset: 0x0000, Name: AFEDIESTA
Table 39. Bit Descriptions for AFEDIESTA
Bits Bit Name Settings
[15:1] Reserved
0 AFEDIESTA
analog.com
Description
Reserved.
POR Source for Digital Die. This bit contains additional details after a POR occurs.
00 POR triggered because DVDD drops below POR threshold.
01 POR triggered because DVDD drops below POR threshold.
10 POR triggered because DVDD_REG supply drops below 1.08 V.
11 POR triggered because DVDD_REG drops below fail-safe.
Software Reset. Set automatically to 1 when the Arm Cortex-M3 system reset is generated. Cleared by
writing 1 to the bit.
Reserved.
External Reset. Set automatically to 1 when an external reset occurs. Cleared by writing 1 to the bit.
POR. Set automatically when a POR occurs. Cleared by writing 1 to the bit.
Description
Reserved.
Watchdog Timeout. Set automatically to 1 when a watchdog timeout occurs. Cleared by writing 1 to the
bit.
External Reset. Set automatically to 1 when an external reset occurs. Cleared by writing 1 to the bit.
AFE POR. Set automatically when a POR occurs. Cleared by writing 1 to the bit.
Description
Reserved.
Status of AFE to Digital Die Communication Status After a Reset Sequence. Always read this bit
after every reset.
0 Analog die trimming and calibration has been confirmed.
1 Analog die is not configured correctly and must not be used.
ADuCM356
Reset Access
0x0 R
R/W
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
Reset Access
0xX R
0xX R/W1C
0xX R/W1C
0xX R/W1C
Reset Access
0x0 R
0x0 R
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