Reference Manual
REGISTER DETAILS: DIGITAL INPUTS AND OUTPUTS
GPIO PORT INTERRUPT B ENABLE REGISTERS
Address: 0x4002002C, Reset: 0x0000, Name: GP0IENB
Address: 0x4002006C, Reset: 0x0000, Name: GP1IENB
Address: 0x400200AC, Reset: 0x0000, Name: GP2IENB
Table 270. Bit Descriptions for GP0IENB, GP1IENB, GP2IENB
Bits
Bit Name
[15:0]
INTBEN
GPIO PORT INTERRUPT STATUS REGISTERS
Address: 0x40020030, Reset: 0x43C0, Name: GP0INT
Address: 0x40020070, Reset: 0x7800, Name: GP1INT
Address: 0x400200B0, Reset: 0x4, Name: GP2INT
Table 271. Bit Descriptions for GP0INT, GP1INT, GP2INT
Bits
Bit Name
Settings
[15:0]
INTSTATUS
GPIO PORT DRIVE STRENGTH SELECT REGISTERS
Address: 0x40020034, Reset: 0x0000, Name: GP0DS
Address: 0x40020074, Reset: 0x0000, Name: GP1DS
Address: 0x400200B4, Reset: 0x0000, Name: GP2DS
Table 272. Bit Descriptions for GP0DS, GP1DS, GP2DS
Bits
Bit Name
Settings
[15:0]
DS
AFE GPIO PORT CONFIGURATION REGISTER
Address: 0x400C0080, Reset: 0x00, Name: CON
Table 273. Bit Descriptions for CON
Bits
Bit Name
[15:4]
Reserved
[3:2]
CON1
[1:0]
CON0
analog.com
Settings
Description
GPIO Pin Interrupt B Enable Register.
0 Clear this bit to disable the corresponding pin interrupt.
1 Set this bit to enable the corresponding pin interrupt.
Description
GPIO Pin Interrupt Status Register.
0 Indicates no interrupt on the corresponding pin.
1 When set, this bit indicates the corresponding pin interrupt event has been latched. To clear this bit and interrupt
event, write 1 to the same bit. Writing 0 has no effect.
Description
Drive Strength Control. Do not use the bit band alias addresses for this register.
0 Clear this bit for normal drive strength.
1 Set by user code for maximum drive strength capability on the corresponding GPIO pin.
Settings
00 PWM1.
10 GPIO.
00 PWM0.
01 GPIO.
Description
Reserved.
GPIO1/PWM1 Configuration Bits.
GPIO0/PWM0 Configuration Bits.
ADuCM356
Access
R/W
Access
R/W1C
Access
R/W
Reset
Access
0x000
R/W
0x0
R/W
0x0
R/W
Rev. A | 218 of 312
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