Spi Interrupts; Spi Wire-Or'ed Mode - Analog Devices ADuCM356 Reference Manual

Reference Manual
SERIAL PERIPHERAL INTERFACES

SPI INTERRUPTS

There is one interrupt line per SPI and 11 sources of interrupts.
SPIx_STAT, Bit 0 reflects the state of the interrupt line, and
SPIx_STAT, Bits[15:12] and SPIx_STAT, Bits[7:1] reflect the state
of the 11 sources. The SPI generates either transmit or receive
interrupts. Both interrupts cannot be enabled at the same time. The
appropriate interrupt is enabled using SPIx_CTL, Bit 6. If TIM = 1,
the transmit IRQ is enabled. If TIM = 0, the receive IRQ is enabled.
Table 304. SPIx_IEN, Bits[2:0] IRQ Mode Bits
SPIx_IEN, Bits[2:0] Settings
000
001
010
011
100
101
110
111
The interrupts are generated depending on the number of bytes
transmitted and not on the number of bytes in the FIFO. The trans-
mit interrupt is different from the receive interrupt, which depends
on the number of bytes in the receive FIFO and not on the number
of bytes received.
The transmit interrupt is cleared by a read to the status register.
The status of this interrupt can be read by reading SPIx_STAT,
Bit 5. The interrupt is disabled if SPIx_CTL, Bit 13 is left high. A
write to the control register, SPIx_CTL, resets the transmitted byte
counter back to 0. For example, if SPIx_IEN, Bits[2:0] are set to
0x3 and SPIx_CTL is written to after three bytes are transmitted,
the transmit interrupt does not occur until another four bytes are
transmitted.
Receive Interrupt
If the TIM bit (SPIx_CTL, Bit 6) is cleared, the receive FIFO status
causes the receive interrupt to be generated. SPIx_IEN, Bits[2:0]
control when the interrupt occurs. The interrupt is cleared by a read
of the SPIx_STAT register. The status of this interrupt can be read
in SPIx_STAT, Bit 6.
Interrupts are only generated when data is written to the FIFO.
For example, if SPIx_IEN, Bits[2:0] is set to 0b000, an interrupt is
generated after the first byte is received. When the status register
is read, the interrupt is deactivated. If the byte is not read from
the FIFO, the interrupt is not regenerated. Another interrupt is not
generated until another byte is received in the FIFO.
The interrupt depends on the number of valid bytes in FIFO and
not on the number of bytes received. For example, when SPIx_IEN,
Bits[2:0] is set to 0b001, an interrupt is generated after a byte is
received if there are two or more bytes in the FIFO. The interrupt is
analog.com
Interrupt Condition
An interrupt occurs after each byte that is transmitted. The interrupt occurs when the byte is read from the FIFO and written to the
shift register.
An interrupt occurs after every two bytes that are transmitted.
An interrupt occurs after every third byte that is transmitted.
An interrupt occurs after every fourth byte that is transmitted.
An interrupt occurs after every fifth byte that is transmitted.
An interrupt occurs after every sixth byte that is transmitted.
An interrupt occurs after every seventh byte that is transmitted.
An interrupt occurs after every eighth byte that is transmitted.
In addition, the SPI0 and SPI1 interrupt source must be enabled in
the NVIC register as follows: ISER0, Bit 15 = SPI0, ISER0, Bit 16 =
SPI1.
Transmit Interrupt
If SPIx_CTL, Bit 6 is set, the transmit FIFO status causes the
interrupt. The SPIx_IEN, Bits[2:0] control when the interrupt occurs,
as shown in Table 304.
not generated after every two bytes received. The receive interrupt
is disabled if SPIx_CTL, Bit 12 is left high.
Underrun and Overflow Interrupts
SPIx_STAT, Bit 7 and SPIx_STAT, Bit 4 generate SPI interrupts.
When a transfer starts with no data in the transmit FIFO,
SPIx_STAT, Bit 4 is set to indicate an underrun condition, which
causes an interrupt. The interrupt and status bits are cleared upon
a read of the status register. This interrupt occurs irrespective of
SPIx_IEN, Bits[2:0]. This interrupt is disabled if SPIx_CTL, Bit 13 is
set.
When data is received and the receive FIFO is already full,
SPIx_STAT, Bit 7 is set to 1, indicating an overflow condition, which
causes an interrupt. The interrupt and status bit are cleared upon
a read of the status register. This interrupt occurs irrespective of
SPIx_CTL, Bits[2:0]. This interrupt is disabled if SPIx_CTL, Bit 12 is
set.
When the SPI receive overflow bit (SPIx_STAT, Bit 7) is set to 1,
the contents of the SPI receive FIFO are undetermined and must
not be used. The user must flush the receive FIFO upon detecting
this error condition. All interrupts are cleared either by a read of the
status register or when SPIx_CTL, Bit 0 is cleared to 0. The receive
and transmit interrupts are also cleared if the relevant flush bits are
asserted. Otherwise, the interrupts remain active even if the SPI is
reconfigured.

SPI WIRE-OR'ED MODE

To prevent contention when the SPI is used in a multiinitiator or
multitarget system, the data output pins, MOSI and MISO, can be
configured to behave as open circuit drivers. An external pull-up
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