Afe Interrupts; Interrupt Controller Interrupts; Configuring The Interrupts; Custom Interrupts - Analog Devices ADuCM356 Reference Manual

Reference Manual

AFE INTERRUPTS

There are interrupt options available on the ADuCM356 analog
front end that can be configured to toggle the internal GPIO pin
on the digital die. The GPIO pin is connected internally and is not
bonded out of the LGA package.

INTERRUPT CONTROLLER INTERRUPTS

The interrupt controller is divided into two blocks. Each block
consists of an INTCSELx register and an INTCFLAGx register.
Only INTCSEL0 interrupts are connected to the digital die by the
internal GPIO pin. The INTCSEL1 interrupts are only used for
polling. The INTCPOL and INTCCLR registers are common to both
blocks. When an interrupt is enabled in the INTCSELx register, the
corresponding bit in the INTCFLAGx register is set. The available
interrupt sources are shown in

CONFIGURING THE INTERRUPTS

The first step to configure the INTC interrupts is to configure the
digital die GPIO pin that connects internally to the AFE interrupt
controller output. To configure the GPIO pin, take the following
steps:
1. Configure the internal GPIO2 Pin 1 as a GPIO as follows:
DioCfgPin(pADI_GPIO2, PIN1, 0);
2. Configure the internal P2.1 pin as an input as follows:
Table 173. Interrupt Sources Summary
INTCFLAGx Register Flag Name
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
FLAG13
FLAG15
FLAG16
FLAG17
FLAG23
FLAG24
FLAG25
FLAG26
FLAG27
FLAG29
FLAG31
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Table 173.
Interrupt Source Description
ADC result IRQ status.
DFT result IRQ status.
Sinc2 filter result ready IRQ status.
Temperature result IRQ status.
ADC minimum fail IRQ status.
ADC maximum fail IRQ status.
ADC delta fail IRQ status.
Mean IRQ status.
Bootload done IRQ status.
End of sequence IRQ status.
Sequencer timeout finished IRQ status (see the
Sequencer timeout command error IRQ status (see the
Data FIFO full IRQ status.
Data FIFO empty IRQ status.
Data FIFO threshold IRQ status, threshold value set in DATAFIFOTHRES register.
Data FIFO overflow IRQ status.
Data FIFO underflow IRQ status.
Outlier IRQ status, detects when an outlier is detected.
Attempt to break IRQ status. This interrupt is set if a Sequence B request occurs when Sequence A is running. This interrupt
indicates that Sequence B is ignored.
DioIenPin(pADI_GPIO2, PIN1, 1); /* Enable
P2.1 input path. */
3. Enable External Interrupt 3 and configure for falling edge as
follows:
EiCfg(EXTINT3, INT_EN, INT_FALL); /* Fall►
ing edge. */
4. Enable the interrupt in the NVIC as follows:
NVIC_EnableIRQ(AFE_EVT3_IRQn);
When these steps are complete, the digital die is configured for
INTC interrupts. To configure the AFE INTC interrupts, first write
to the INCT0POL to configure the polarity. To enable the required
interrupt, write to the INTCSEL0 register. To clear an interrupt
source, write to the corresponding bit in the INTCCLR register.

CUSTOM INTERRUPTS

Four custom interrupt sources are selectable by the user in the
INTCSELx register, Bits[12:9]. For these custom interrupts to gen-
erate an interrupt event, write to the corresponding bit in the
AFEGENINTSTA register. It is only possible to write to this register
via the sequencer.
Timer Command section).
Timer Command section).
ADuCM356
Rev. A | 136 of 312