Clear Interrupt Register; 16-Bit Load Value, Asynchronous Register; 16-Bit Timer Value, Asynchronous Register - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: ANALOG DIE GENERAL-PURPOSE TIMERS
Table 365. Bit Descriptions for CTL (Continued)
Bits Bit Name Settings
4 EN
3 MODE
2 UP
[1:0] PRE

CLEAR INTERRUPT REGISTER

Address: 0x400C0E0C, Reset: 0x0000, Name: CLRINT
Table 366. Bit Descriptions for CLRINT
Bits Bit Name Settings
[15:2] Reserved
1 EVTCAPT
0 TIMEOUT

16-BIT LOAD VALUE, ASYNCHRONOUS REGISTER

Address: 0x400C0E14, Reset: 0x0000, Name: ALOAD
Only use when a synchronous clock source is selected (CTL, Bits[6:5] = 00).
Table 367. Bit Descriptions for ALOAD
Bits Bit Name Settings
[15:0] VALUE

16-BIT TIMER VALUE, ASYNCHRONOUS REGISTER

Address: 0x400C0E18, Reset: 0x0000, Name: ACURCNT
Only use when a synchronous clock source is selected (CTL, Bits[6:5] = 00).
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Description
Timer Enable. Used to enable and disable the timer. Clearing this bit resets the timer, including the
CURCNT register.
0 Timer is disabled. Default.
1 Timer is enabled.
Timer Mode. This bit is used to control whether the timer runs in periodic or free running mode. In
periodic mode, the up or down counter starts at the defined ALOAD, Bits[15:0]. In free running mode, the
up or down counter starts at 0x0000 or 0xFFFF, depending on whether the timer is counting up or down.
1 Timer runs in periodic mode. Default.
0 Timer runs in free running mode.
Count Up. Used to control whether the timer increments (counts up) or decrements (counts down) the up
or down counter.
1 Timer is set to count up.
0 Timer is set to count down. Default.
Prescaler. Controls the prescaler division factor applied to the selected clock of the timer.
00 Source clock/1 or source clock/4. When CTL, Bit 15 is set, source clock/1. When cleared, source clock/4.
01 Source clock/16.
10 Source clock/64.
11 Source clock/256.
Description
Reserved.
Clear Captured Event Interrupt. This bit is used to clear a capture event interrupt.
1 Clear the capture event interrupt.
0 No effect.
Clear Timeout Interrupt. This bit is used to clear a timeout interrupt.
1 Clears the timeout interrupt.
0 No effect.
Description
Load Value, Asynchronous. The up or down counter is periodically loaded with this value if periodic mode
is selected (CTL, Bit 5 = 1). Writing this register takes advantage of having the timer run on PCLK by
bypassing clock synchronization logic that is otherwise required.
ADuCM356
Reset Access
0x0 R/W
0x1 R/W
0x0 R/W
0x2 R/W
Reset Access
0x0 R
0x0 W1C
0x0 W1C
Reset Access
0x0 R/W
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