User Manuals: Analog Devices ADRV9003 RF Transceiver

Manuals and User Guides for Analog Devices ADRV9003 RF Transceiver. We have 2 Analog Devices ADRV9003 RF Transceiver manuals available for free PDF download: Reference Manual, User Manual

Analog Devices ADRV9003 Reference Manual

Analog Devices ADRV9003 Reference Manual (377 pages)

Brand: Analog Devices | Category: Motherboard | Size: 30 MB

Table of Contents

ADRV9001 System Development User Guide Overview
1
Changes to ADRV9001 System Development User Guide Overview Section
1
Table of Contents
2
How to Use this Document
7
Block Diagram
8
Product Highlights
9
- Adrv9002
  9
- Adrv9003
  11
- Adrv9004
  11
- Adrv9005
  11
- Adrv9006
  11
Added ADRV9005 Section
11
Added ADRV9006 Section
11
- ADRV9001 Product Family Comparison
  12
- Added ADRV9001 Product Family Comparison Section and Table 1; Renumbered Sequentially
  12
ADRV9001 Example Use Cases
13
Software System Architecture Description
33
Software Integration
38
- Hardware Abstraction Layer
  38
- Developing the Application
  43
System Initialization and Shutdown
45
- TES Configuration and Initialization
  45
- API Initialization Sequence
  46
Changes to API Initialization Sequence Section
46
- State Change Timing
  48
- Shutdown Sequence
  48
- System Debugging
  48
- Warm Boot
  50
- Changes to Warm Boot Section and Table 15
  50
- Boot-Up Timing
  52
Added Operating Temperature Considerations Section
52
Changes to Table 16
54
Changes to Warm Boot Boot-Up Section
55
Added Table 17
55
Serial-Peripheral Interface (SPI)
56
- SPI Configuration
  56
- SPI Bus Signals
  56
- SPI Broadcast Mode
  57
- Added SPI Broadcast Mode Section and Figure 27; Renumbered Sequentially
  57
- SPI Data Transfer Protocol
  58
- Added Table 19
  58
- Timing Diagrams
  60
Changes to Timing Diagrams Section
60
- SPI Test
  61
- SPI Main
  61
Data Interface
64
Changes to Enhanced Rx SSI Mode Section
76
- Power Saving for LSSI
  77
- SSI Timing Parameters
  77
- Added Figure 58
  77
- API Programming
  78
- CSSI/LSSI Testability and Debug
  80
Microprocessor and System Control
83
- System Control
  84
- Timing Parameters Control
  84
- API Execution Timing
  98
Clock Generation
99
- Low Power Clock Phase-Lock Loop (LP CLKPLL)
  99
- Arbitrary Sample Rate
  100
Multichip Synchronization
102
- Introduction
  102
- Theory of Operation
  102
- MCS Substates (Internal MCS State Transition)
  105
- MCS Procedure and Status Check
  105
Changes to MCS Procedure and Status Check Section
105
- Sample Delay and Read Delay
  106
- Phase Synchronization
  108
Changes to RF Synthesizer Section
110
Synthesizer Configuration and lo Operation
110
- Clock Synthesizer
  110
- RF Synthesizer
  110
Added RF Synthesizer Frequency Accuracy Section
111
Added Example Frequency Accuracy Calculation Section
111
- Auxiliary Synthesizer
  112
- External lo
  112
- RF PLL Loop Filter Recommendations
  112
- PLL Phase Noise
  112
- API Operation
  114
Changes to Local Oscillator (LO) Change Procedure Section
114
Frequency Hopping
116
- Key Signals
  116
- Modes of Operation
  117
- Changes to Modes of Operation Section and Table 48
  117
- Frequency Hopping Table
  119
Changes to Example 1: Load New Frequencies with Automatic Ping Pong Section
122
Changes to Example 2: Loading a Larger Set of Frequencies with Manual Table Switch Section
123
- Selecting the Channel and Profile
  124
- Frequency Hopping Operation Ranges
  124
- Frequency Hopping Calibrations
  124
- Frequency Hopping Timing
  125
- Additional Frequency Hopping Operations
  132
- Diversity Mode
  136
- Frequency Hopping with Rx/Orx Gain Control
  137
- Special Frequency Hopping Operations
  137
- Integration with Other Advanced Features
  140
- Frequency Hopping API Programming
  141
Transmitter Signal Chain
142
- Data Interface
  142
- Datapath
  142
- Digital Front End (DFE)
  143
- Analog Front End (AFE)
  148
- Transmit Data Chain API Programming
  149
Receiver/Observation Receiver Signal Chain
150
- Receive Data Chain
  152
- Analog Front-End Components
  153
- Digital Front End Components
  155
- Receive Data Chain API Programming
  159
Transmitter/Receiver/Observation Receiver Signal Chain Calibrations
161
- Initial Calibrations
  161
- Tracking Calibrations
  172
Receiver Gain Control
177
- Receiver Datapath
  178
- Gain Control Modes
  183
- Gain Control Detectors
  190
- AGC Clock and Gain Block Timing
  194
- Analog Gain Control API Programming
  195
- Digital Gain Control and Interface Gain (Slicer)
  202
- Digital Gain Control and Interface Gain API Programming
  205
- Usage Recommendations
  206
- TES Configuration and Debug Information
  206
Receiver Demodulator
211
Power Saving and Monitor Mode
218
- Power-Down Modes
  218
- Power-Down/Up Channel in Calibrated State
  219
- Dynamic Interframe Power Saving
  219
- Monitor Mode
  222
Digital Predistortion (DPD)
230
- Background
  230
- ADRV9001 DPD Function
  230
- ADRV9001 DPD Supported Waveforms
  231
- DPD with Frequency Hopping (FH)
  232
- ADRV9001 DPD Performance
  232
- Closed Loop Gain Control (CLGC)
  233
- DPD/CLGC Configuration
  234
- Board Configuration
  244
- Save and Load DPD Coefficients from Last Transmission
  245
- Define the Frequency Region When Performing DPD with FH
  245
- DPD/CLGC API Programming
  246
- DPD Tuning and Testing
  246
- Measuring the CLGC Target Gain
  249
Dynamic Profile Switching (DPS)
251
- Overview
  251
- Initial Calibration with DPS
  251
- Performing DPS on the Fly
  252
- DPS API Programming
  253
- Summary of DPS Limitations
  253
- DPS Operations in TES
  254
Power Amplifier Ramp Control
256
- Power Amplifier Open-Loop Ramp Control
  256
- Power Amplifier Close Loop Ramp Control
  257
General-Purpose Input/Output (GPIO) and Interrupt Configuration
258
- GPIO Operation
  259
- Analog GPIO Operation
  262
- Interrupt
  263
Auxiliary Converters and Temperature Sensor
264
RF Port Interface Information
267
- Transmit Ports: TX1± and TX2
  267
- Receive Ports: RX1A±, RX1B±, RX2A±, and RX2B
  267
- External Local Oscillator Ports: LO1± and LO2
  267
- Device Clock Port: DEV_CLK1
  267
- RF Receiver/Transmitter Ports Impedance Data
  267
- General Receiver Port Interface
  270
- General Transmitter Bias and Port Interface
  273
- Impedance Matching Network Examples
  275
- Receiver RF Port Impedance Matching Network
  276
  - Measurement Data
    279
  - Network
    280
  - Measurement Data
    282
  - Network
    283
  - Measurement Data
    286
  - (Dev_Clk_In)
    286
- DEV_CLK_IN Phase Noise Requirements
  288
  - (MCS) Input
    289
- Recommendations
  290
- Selecting the PCB Material and Stackup
  290
- Fanout and Trace Space Guidelines
  291
- Component Placement and Routing Priorities
  292
- Isolation Techniques Used on the
  305
- Transmitter RF Port Impedance Matching ADRV9001 Evaluation Card
  305
Power-Supply Recommendations
308
ADRV9001 Evaluation System
329
Printed Circuit Board Layout Additional Resources
375
- Q Formatting Standard Description
  375
- Frequently Asked Questions
  376

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Analog Devices ADRV9003 User Manual

Analog Devices ADRV9003 User Manual (338 pages)

Brand: Analog Devices | Category: Microcontrollers | Size: 18 MB

Table of Contents

Table of Contents
2
How to Use this Document
5
Block Diagram
6
Product Highlights
7
- Adrv9002
  7
- Bandwidth and Sample Rate Support
  7
- Adrv9003
  9
- Adrv9004
  9
ADRV9001 Example Use Cases
10
Software System Architecture Description
30
- Software Architecture
  30
- Folder Structure
  31
Customising the System Architecture and File Structure
32
Software Integration
35
- Hardware Abstraction Layer
  35
- Developing the Application
  41
System Initialization and Shutdown
43
Serial Peripheral Interface (SPI)
47
- SPI Configuration
  47
- SPI Bus Signals
  48
- SPI Data Transfer Protocol
  48
- Timing Diagrams
  50
- SPI Test
  51
Data Interface
52
- General Description
  52
- Electrical Specification
  52
- CMOS Synchronous Serial Interface (CMOS-SSI)
  54
- LVDS Synchronous Serial Interface (LVDS-SSI)
  61
- Enhanced Rx SSI Mode
  64
- Power Saving for LSSI
  65
- SSI Timing Parameters
  65
- API Programming
  65
- CSSI/LSSI Testability and Debug
  68
Microprocessor and System Control
70
- System Control
  71
- Timing Parameters Control
  71
Clock Generation
86
Multichip Synchronization
88
- Introduction
  88
- Theory of Operation
  88
- MCS Substates (Internal MCS State Transition)
  91
- Procedure
  91
- Sample Delay and Read Delay
  92
- Phase Synchronization
  94
Synthesizer Configuration and lo Operation
96
- Clock Synthesizer
  96
- RF Synthesizer
  96
- Auxiliary Synthesizer
  97
- External lo
  97
- API Operation
  99
Frequency Hopping
102
- Key Signals
  102
- Modes of Operation
  105
- Channel and Profile Selection
  106
- Frequency Hopping Operation Ranges
  107
- Frequency Hopping Table
  107
- Frequency Hopping Calibrations
  111
- Frequency Hopping Timing
  113
- Additional Frequency Hopping Operations
  117
- Diversity Mode
  121
- Frequency Hopping with Rx/Orx Gain Control
  121
- Integration with Other Advanced Features
  122
Transmitter Signal Chain
123
- Data Interface
  123
- Datapath
  124
- Digital Front End (DFE)
  124
- Analog Front End (AFE)
  129
- Transmit Data Chain API Programming
  130
Receiver/Observation Receiver Signal Chain
131
- Receive Data Chain
  133
- Analog Front-End Components
  134
- Lpf
  135
- Adc
  135
- Digital Front End Components
  136
- DC Offset
  136
- Qec
  137
- DDC
  137
- Frequency Offset Correction
  137
- Pfir
  137
- Rssi
  137
- Receive Data Chain API Programming
  138
Transmitter/Receiver/Observation Receiver Signal Chain Calibrations
140
- Initial Calibrations
  140
- Tracking Calibrations
  150
Receiver Gain Control
154
- Receiver Datapath
  155
- Gain Control Modes
  158
- Gain Control Detectors
  166
- AGC Clock and Gain Block Timing
  169
- Analog Gain Control API Programming
  170
- Digital Gain Control and Interface Gain (Slicer)
  177
- Digital Gain Control and Interface Gain API Programming
  179
- Usage Recommendations
  180
- TES Configuration and Debug Information
  181
Rx Demodulator
184
- Rx Narrow-Band Demodulator Subsystem
  184
- Normal IQ Output Mode
  188
- Frequency Deviation Output Mode
  188
- API Programming
  189
Power Saving and Monitor Mode
191
- Power-Down Modes
  191
- Power-Down/Power-Up Channel in Calibrated State
  192
- Dynamic Interframe Power Saving
  192
- Monitor Mode
  194
Digital Predistortion
197
- Background
  197
- ADRV9001 DPD Function
  197
- ADRV9001 DPD Supported Waveforms
  199
- DPD with Frequency Hopping (FH)
  199
- ADRV9001 DPD Performance
  199
- Closed Loop Gain Control (CLGC)
  201
- DPD/CLGC Configuration
  201
- Board Configuration
  210
- Save and Load DPD Coefficients from Last Transmission
  211
- Define the Frequency Region When Performing DPD with FH
  211
- DPD/CLGC API Programming
  212
- DPD Tuning and Testing
  212
- CLGC Target Gain Measurment
  215
Dynamic Profile Switching
216
- Overview
  216
- Initial Calibration with DPS
  216
- Perform DPS on the Fly
  217
- DPS API Programming
  218
- Summary of DPS Limitations
  218
- DPS Operations in TES
  219
General-Purpose Input/Output and Interrupt Configuration
221
- Digital GPIO Operation
  222
- Analog GPIO Operation
  225
- Interrupt
  226
Auxiliary Converters and Temperature Sensor
227
- Auxiliary DAC (Auxdac)
  227
- Auxiliary ADC (Auxadc)
  227
- Temperature Sensor
  228
RF Port Interface Information
229
Printed Circuit Board Layout Recommendations
251
Power Supply Recommendations
269
Power Management Considerations
269
- Power Supply Sequence
  269
- Power Supply Domain Connections
  270
- Power Supply Architecture
  272
- RF and Clock Synthesizer Supplies
  275
Power Supply Configurations
276
Summary
282
LDO Configurations
283
ADRV9001 Evaluation System
290
- Initial Setup
  290
- Hardware Kit
  290
- Hardware Operation
  295
- Transceiver Evaluation Software (TES)
  296
- Automated Time Division Duplexing (TDD)
  317
- Tracking Calibrations
  320
- Digital Predistortion
  321
- TDD Enablement Delays
  321
- Auxiliary DAC/ADC
  321
- Frequency Hopping TES Examples
  322
- Radio State
  331
- Power/Temperature Monitoring
  331
- Driver Debugger
  332
- Log File
  333
- Automatically Generate Initialisation Code
  334
- Evaluation System Troubleshooting
  334

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