Serial Clock Period Divisor Register; Target Control Register - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: I

SERIAL CLOCK PERIOD DIVISOR REGISTER

Address: 0x40003024, Reset: 0x1F1F, Name: DIV
Table 291. Bit Descriptions for DIV
Bits Bit Name Settings
[15:8] HIGH
[7:0] LOW

TARGET CONTROL REGISTER

Address: 0x40003028, Reset: 0x0000, Name: SCTL
Table 292. Bit Descriptions for SCTL
Bits Bit Name Settings
15 Reserved
14 STXDMA
13 SRXDMA
12 IENREPST
11 Reserved
10 IENSTX
9 IENSRX
8 IENSTOP
7 NACK
6 Reserved
5 EARLYTXR
4 GCSBCLR
3 HGCEN
2 GCEN
1 ADR10EN
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2
C
Description
Serial Clock High Time. This register controls the clock high time. The PCLK drives the timer. To derive the
required high time, calculate: High = (REQD_HIGH_TIME/PCLK_PERIOD) – 2. For example, to generate a
400 kHz I2C_SCL with a low time of 1300 ns and a high time of 1200 ns, with a core clock frequency of 26
MHz, Low = 1300 ns/38 ns − 1 = 0x21 (33 decimal). High = 1200 ns/38 ns − 2 = 0x1D (29 decimal). This
register is reset to 0x1F, which gives an I2C_SCL high time of 33 PCLK cycles.
Serial Clock Low Time. This register controls the clock low time. The PCLK drives the timer. To derive the
required low time, calculate: Low = (REQD_LOW_TIME/PCLK_PERIOD) – 1. This register is reset to 0x1F,
which gives an I2C_SCL low time of 32 PCLK cycles.
Description
Reserved.
Enable Target Transmit DMA Request.
0 Disable DMA mode.
2
1 Enable I C target DMA receive requests.
Enable target Receive DMA Request.
0 Disable DMA mode.
2
1 Enable I C target DMA receive requests.
Repeated Start Interrupt Enable.
0 Interrupt not generated when the SSTAT, Bit 13 asserts.
1 Generate interrupt when the SSTAT, Bit 13 asserts.
Reserved.
Target Transmit Request Interrupt Enable.
Target Receive Request Interrupt Enable.
Stop Condition Detected Interrupt Enable.
No Acknowledge Next Communication. If this bit is set, the next communication is not acknowledged.
Reserved. Write 0 to this bit.
Early Transmit Request Mode. Setting this bit enables a transmit request immediately after the positive edge
of the direction bit I2C_SCL clock pulse.
General Call Status Bit Clear.
0 Does not clear general call status and general call ID bits.
1 Clear general call status and general call ID bits. The general call status and general call ID bits are not reset
by anything other than a write to this bit or a full reset.
Hardware General Call Enable. When this bit and the general call enable bit are set, after receiving a general
call, the device and a data byte check the contents of the ALT register against the receive shift register. If
these registers match, the device has received a hardware general call. This call is used if a device requires
urgent attention from an initiator device without knowing which initiator to which to turn. This is a to whom it
may concern call. The device that requires attention embeds its own address into the message. The LSB of
the ALT register must always be written to a 1, as per the I
General Call Enable. This bit enables the I
(write).
Enabled 10-Bit Addressing. If this bit is clear, the target can support four target addresses, programmed in
the ID0 register to the ID3 register. When this bit is set, 10-bit addressing is enabled. One 10-bit address is
2
C January 2000 specification.
2 2
C target to acknowledge an I C general call, Address 0x00
ADuCM356
Reset Access
0x1F R/W
0x1F R/W
Reset Access
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 W
0x0 R/W
0x0 R/W
0x0 R/W
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