Analog Devices ADuCM356 Reference Manual page 138

Reference Manual
AFE INTERRUPTS
Table 176. Bit Descriptions for INTCCLR Register (Continued)
Bits Bit Name Description
6 INTCLR6 ADC Delta Fail IRQ. Write 1 to clear.
5 INTCLR5 ADC Maximum Fail IRQ. Write 1 to clear.
4 INTCLR4 ADC Minimum Fail IRQ. Write 1 to clear.
3 INTCLR3 Temperature Result IRQ. Write 1 to clear.
2 INTCLR2 Sinc2 Filter Result Ready IRQ. Write 1 to clear.
1 INTCLR1 DFT Result IRQ. Write 1 to clear.
0 INTCLR0 ADC Result IRQ. Write 1 to clear.
Interrupt Controller Select Registers
Address: 0x400C3008, Reset: 0x00002000, Name: INTCSEL0
Address: 0x400C300C, Reset: 0x00002000, Name: INTCSEL1
Table 177. Bit Descriptions for INTCSEL0 and INTCSEL1 Registers
Bits Bit Name
31 INTSEL31
30 Reserved
29 INTSEL29
28 Reserved
27 INTSEL27
26 INTSEL26
25 INTSEL25
24 INTSEL24
23 INTSEL23
[22:18] Reserved
17 INTSEL17
16 INTSEL16
15 INTSEL15
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Settings Description
Attempt to Break IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Reserved.
Outlier IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Reserved.
Data FIFO Underflow IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Data FIFO Overflow IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Data FIFO Threshold IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Data FIFO Empty IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Data FIFO Full IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Reserved.
Sequencer Timeout Error IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Sequencer Timeout Finished IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
End of Sequence IRQ Enable.
0 Interrupt disabled.
ADuCM356
Reset Access
0x0 W
0x0 W
0x0 W
0x0 W
0x0 W
0x0 W
0x0 W
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Rev. A | 138 of 312
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W