Spi Transfer Initiation - Analog Devices ADuCM356 Reference Manual

Reference Manual
SERIAL PERIPHERAL INTERFACES
In SPI initiator mode, CS is an active low output signal. The
pin asserts itself automatically at the beginning of a transfer and
deasserts itself upon completion.
If an ADuCM356 initiator wants to communicate with multiple SPI
targets, GPIOs can be connected to the chip select lines of the
targets. Use the CSRISE and CSFALL bits (SPIx_STAT, Bit 13
and SPIx_STAT, Bit 14, respectively) to determine when to pull the
GPIOs low or high.

SPI TRANSFER INITIATION

In initiator mode, the transfer and interrupt mode bit (SPIx_CTL,
Bit 6) determines the manner in which an SPI serial transfer is
initiated. If this bit is set, a serial transfer is initiated after a write to
the transmit FIFO. If this bit is cleared, a serial transfer is initiated
after a read of the receive FIFO. The read must be performed while
the SPI interface is idle. A read performed during an active transfer
does not initiate another transfer.
For any setting of SPIx_CTL, Bit 1 and SPIx_CTL, Bit 6, the
SPI simultaneously receives and transmits data. Therefore, during
data transmission, the SPI is also receiving data and filling up the
receive FIFO. If the data is not read from the receive FIFO, the
overflow interrupt occurs when the FIFO starts to overflow. If the
user does not want to read the receive data or receive overflow
interrupts, set SPIx_CTL, Bit 12 and the receive data is not saved
to the receive FIFO. Similarly, to only receive data and not write
data to the transmit FIFO, set SPIx_CTL, Bit 13 to avoid receiving
underrun interrupts from the transmit FIFO.
Transmit Initiated Transfer
For transfers initiated by a write to the transmit FIFO, the SPI
starts transmitting as soon as the first byte is written to the FIFO,
irrespective of the configuration in SPIx_IEN, Bits[2:0]. The first
byte is immediately read from the FIFO, written to the transmit shift
register, and the transfer commences.
If the continuous transfer enable bit, SPIx_CTL, Bit 11, is set, the
transfer continues until no valid data is available in the transmit
FIFO. This completion is either the end of SPIx_CNT, Bits[13:0]
number of bytes (if SPIx_CNT, Bits[13:0] > 0) or when no valid data
is available in the transmit FIFO (if SPIx_CNT, Bits[13:0] = 0). Chip
select remains asserted for the duration of the complete transfer.
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If SPIx_CNT, Bit 15 is cleared and SPIx_CNT, Bits[13:0] > 0, the
transfer stops when all the bytes in SPIx_CNT, Bits[13:0] have been
transferred. If SPIx_CNT, Bit 15 is set, a new frame starts after
every SPIx_CNT, Bits[13:0] number of bytes. Multiples of bytes in
SPIx_CNT, Bits[13:0] are always transferred in this case. If there is
no data or space in the FIFO, the transfer stalls until it is available.
Conversely, the transfer continues while there is valid data in the
FIFO. If SPIx_CTL, Bit 11 is cleared, each transfer consists of a
single 8-bit serial transfer. If valid data exists in the transmit FIFO,
a new transfer is initiated after a stall period, and a chip select is
deasserted.
Receive Initiated Transfer
Transfers initiated by a read of the receive FIFO depend on the
number of bytes received in the FIFO. If SPIx_IEN, Bits[2:0] =
0b111 and a read to the receive FIFO occurs, the SPI initiates
an 8-byte transfer. If continuous mode is set (SPIx_CTL, Bit 11 =
1), the eight bytes occur continuously with no deassertion of chip
select between bytes. However, in continuous mode, if SPIx_CNT,
Bits[13:0] > 0, the chip select asserts for the entire frame duration.
The SPI introduces stall periods by not clocking SPI0_CLK or
SPI1_CLK until FIFO space is available. If continuous mode is not
set, the eight bytes occur with stall periods between transfers where
the chip select output is deasserted.
If SPIx_IEN, Bits[2:0] = 0b110, a read of the receive FIFO initiates a
7-byte transfer. If SPIx_IEN, Bits[2:0] = 0b001, a read of the receive
FIFO initiates a 2-byte transfer. If SPIx_IEN, Bits[2:0] = 0b000,
a read of the receive FIFO initiates a 1-byte transfer. A read of
the receive FIFO while the SPI is receiving data does not initiate
another transfer after the present transfer is complete.
In continuous mode, if SPIx_CNT, Bits[13:0] > 0 and SPIx_CNT,
Bit 15 = 1, a read of the receive FIFO at the end of an SPI frame
always initiates a new SPI frame. To stop SPI transfers at any given
frame, clear the SPIx_CNT, Bit 15 before reading the final set of
receive bytes.
The SPI transfer protocol diagrams illustrate the data transfer
protocol for the SPI and the effects of the CPHA and CPOL bits in
the control register (SPIx_CTL) on that protocol. See
Figure 62.
ADuCM356
Figure 61 and
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