Analog Devices ADuCM355 Manuals

Manuals and User Guides for Analog Devices ADuCM355. We have 2 Analog Devices ADuCM355 manuals available for free PDF download: Hardware Reference Manual, Diagrams

Analog Devices ADuCM355 Hardware Reference Manual (312 pages)

Brand: Analog Devices | Category: Microcontrollers | Size: 1 MB

Scope
1
Table of Contents
2
Revision History
9
Using the Aducm355 Reference Manual
11
Introduction to the Aducm355
12
Main Features of the Aducm355
12
Clocking Architecture
14
Clocking Architecture Operation
14
Required Clock Ratio between Digital die and Analog die System Clocks
14
Digital die Clock Features
14
Analog die Clock Features
14
Clock Gating
15
Connecting AFE die Clock to Digital die Clock Input
15
Register Summary: Clock Architecture
17
Register Details: Clock Architecture
18
Key Protection for CTL Register
18
Oscillator Control Register
18
Clock Control 0 Register
18
Clock Dividers Register
19
User Clock Gating Control Register
19
Clocking Status Register
20
Clock Divider Configuration Register
21
Clock Gate Enable Register
21
Clock Select Register
22
GPIO Clock Mux Select to GPIO1 Pin Register
22
Key Protection for CLKCON0 Register
22
Clock Control of Low Power TIA Chop, Watchdog, and Wake-Up Timers Register
23
Key Protection for OSCCON Register
23
Oscillator Control Register
23
High Power Oscillator Configuration Register
24
Power Mode Configuration Register
24
Power Management Unit
25
Power Management Unit Features
25
Power Management Unit Operation
26
Code Examples
27
Monitor Voltage Control
28
Register Summary: Power Management Unit
29
Register Details: Power Management Unit
30
Power Supply Monitor Interrupt Enable Register
30
Power Supply Monitor Status Register
30
Power Mode Register
31
Key Protection for PWRMOD and SRAMRET Register
31
Control for Retention SRAM During Hibernate Mode Register
32
HPBUCK Control Register
32
Control for SRAM Parity and Instruction SRAM Register
32
Initialization Status Register
33
Power Modes Register
34
Key Protection for PWRMOD Register
34
Arm Cortex-M3 Processor
35
Arm Cortex-M3 Processor Features
35
Arm Cortex-M3 Processor Operation
36
Arm Cortex-M3 Processor Related Documents
36
System Resets
37
Digital die Reset Operation
37
Register Summary: System Resets
39
Register Details: System Resets
40
Digital die Reset Status Register
40
Always on Reset Status Register
40
Analog die Status Register
40
Programming, Protection, and Debug
41
Booting
41
Security Features
41
Safety Features
41
System Exceptions and Peripheral Interrupts
42
Cortex-M3 and Fault Management
42
Interrupt Sources from the Analog die
44
Clearing Analog die Interrupt Sources
45
Cortex-M3 NVIC Register List
46
External Interrupt Configuration
47
Register Summary: System Exceptions and Peripheral Interrupts
48
Register Details: System Exceptions and Peripheral Interrupts
49
External Interrupt Configuration 0 Register
49
External Wake-Up Interrupt Status Register
50
External Interrupt Clear Register
50
Nonmaskable Interrupt Clear Register
50
Analog die Interrupt Enable Register
51
Analog die Circuitry Summary
52
ADC, High Speed DAC, and Associated Amplifiers Operating Mode Configuration
52
System Bandwidth Configuration
52
Register Summary: Analog die Circuitry
54
Register Details: Analog die Circuitry
55
AFE Configuration Register
55
ADC Circuit
57
ADC Circuit Overview
57
ADC Circuit Features
57
ADC Circuit Operation
58
ADC Transfer Function
58
ADC Low Power Current Input Channels
59
ADC Input Circuit
60
ADC Postprocessing Filter Options
60
Averaging, Statistics, and Outlier Detection Options
61
Internal Temperature Sensor Channels
62
ADC Initialization
63
ADC Calibration
64
ADC Digital Signal Processor (DSP) Built in Self Test
65
Voltage Reference Options
66
Register Summary: ADC Circuit
67
Register Details: ADC Circuit
69
ADC Configuration Register
69
ADC Output Filters Configuration Register
70
Raw Result Register
71
DFT Result, Real Part Register
71
DFT Result, Imaginary Part Register
72
Sinc2 and Supply Rejection Filter Result Register
72
Temperature Sensor 0 Result Register
72
Analog Capture Interrupt Enable Register
72
Analog Capture Interrupt Register
73
AFE DSP Configuration Register
74
Temperature Sensor 0 Configuration Register
75
High Power and Low Power Buffer Control Register
75
Number of Repeat ADC Conversions Register
76
Buffer Configuration Register
76
Calibration Lock Register
76
Offset Calibration LPTIA0 Channel Register
77
Gain Calibration for LPTIA0 Channel Register
77
Offset Calibration LPTIA1 Channel Register
77
Gain Calibration for LPTIA1 Channel Register
77
Offset Calibration High Speed TIA Channel Register
78
Gain Calibration for High Speed TIA Channel Register
78
Offset Calibration Voltage Channel (PGA Gain = 1) Register
78
Gain Calibration Voltage Input Channel (PGA Gain = 1) Register
79
Offset Calibration Voltage Channel (PGA Gain = 1.5) Register
79
Gain Calibration Voltage Input Channel (PGA Gain = 1.5) Register
79
Offset Calibration Voltage Input Channel (PGA Gain = 2) Register
80
Gain Calibration Voltage Input Channel (PGA Gain = 2) Register
80
Offset Calibration Voltage Input Channel (PGA Gain = 4) Register
80
Gain Calibration Voltage Input Channel (PGA Gain = 4) Register
81
Offset Calibration Voltage Input Channel (PGA Gain = 9) Register
81
Gain Calibration Voltage Input Channel (PGA Gain = 9) Register
81
Offset Calibration Temperature Sensor Channel 0 Register
82
Gain Calibration Temperature Sensor Channel 0 Register
82
Minimum Value Check Register
82
Minimum Slow Moving Value Register
82
Maximum Value Check Register
83
Maximum Slow Moving Register
83
Delta Check Register
83
Statistics Module Configuration Register
83
Mean Output Register
84
Key Access for DSPUPDATEEN Register
84
Digital Logic Test Enable Register
84
Temperature Sensor 1 Control Register
84
Low Power Potentiostat Amplifiers and Low Power Tias
85
Low Power Potentiostat Amplifiers
85
Low Power Tias
85
Low Power Dacs
88
Register Summary: Low Power Tia/Potentiostat and DAC Circuits
92
Register Details: Low Power Tia/Potentiostat and DAC Circuits
93
Low Power TIA Control Bits Channel 0 Register
93
Low Power TIA Switch Configuration for Channel 0 Register
94
Low Power TIA Control Bits Channel 1 Register
95
Low Power TIA Switch Configuration for Channel 1 Register
97
LPDAC0 Data out Register
98
LPDAC0 Switch Control Register
98
LPDAC0 Control Register
99
LPDAC1 Data out Register
99
LPDAC1 Switch Control Register
100
LPDAC1 Control Register
100
Low Power Reference Control Register
101
High Speed TIA Circuits
102
Key Features
102
Using DE0 and DE1 Inputs with the High Speed TIA
104
External RTIA Selection
104
Register Summary: High Speed TIA Circuits
105
Register Details: High Speed TIA Circuits
106
High Speed RTIA Configuration Register
106
DE1 High Speed TIA Resistor Configuration Register
106
DE0 High Speed TIA Resistor Configuration Register
107
High Speed TIA Amplifier Configuration Register
107
High Speed DAC Circuits
108
High Speed DAC Output Signal Generation
108
High Speed DAC Core Power Modes
108
Recommended Configuration in Hibernate Mode
109
High Speed DAC Filter Options
109
High Speed DAC Output Attenuation Options
109
Coupling an AC Signal from High Speed DAC Onto the DC Level Set by Low Power DAC
109
Avoiding Incoherency Errors between Excitation and Measurement Frequencies During Impedance Measurements
110
Calibrating the High Speed DAC
110
Register Summary: High Speed DAC Circuits
112
Register Details: High Speed DAC Circuits
113
High Speed DAC Configuration Register
113
Direct Write to DAC Output Control Value Register
113
DAC DC Buffer Configuration Register
113
DAC Gain Register
114
DAC Offset with Attenuator Enabled (Low Power Mode) Register
114
DAC Offset with Attenuator Disabled (Low Power Mode) Register
114
DAC Offset with Attenuator Enabled (High Power Mode) Register
115
DAC Offset with Attenuator Disabled (High Power Mode) Register
115
Waveform Generator Configuration Register
115
Waveform Generator for Sinusoid Frequency Control Word Register
116
Waveform Generator for Sinusoid Phase Offset Register
116
Waveform Generator for Sinusoid Offset Register
116
Waveform Generator for Sinusoid Amplitude Register
116
Programmable Switches Connecting the External Sensor to the High Speed DAC and High Speed TIA
117
DX Switches
117
Px Switches
117
Nx Switches
117
Tx Switches
117
Options for Controlling All Switches
117
Register Summary: Programmable Switches
120
Register Details: Programmable Switches
121
Switch Matrix Configuration Register
121
DX Switch Matrix Full Configuration Register
122
Nx Switch Matrix Full Configuration Register
123
Px Switch Matrix Full Configuration Register
124
Tx Switch Matrix Full Configuration Register
125
DX Switch Matrix Status Register
126
Px Switch Matrix Status Register
126
Nx Switch Matrix Status Register
127
Tx Switch Matrix Status Register
128
Sequencer
130
Sequencer Features
130
Sequencer Overview
130
Sequencer Commands
130
Sequencer Operation
131
Sequencer and FIFO Registers
134
AFE Interrupts
139
Interrupt Controller Interupts
139
Configuring the Interrupts
139
Custom Interrupts
139
Interrupt Registers
140
Sleep and Wake-Up Timer
145
Sleep and Wake-Up Timer Features
145
Sleep and Wake-Up Timer Overview
145
Configuring a Defined Sequence Order
145
Recommended Sleep and Wake-Up Timer Operation
146
Sleep and Wake-Up Timer Registers
146
Use Case Configurations
150
Hibernate Mode While Maintaining a DC Bias to the Sensor
150
Measuring a DC Current Output
152
Pulse Test (Chronoamperometry)
153
Cyclic Voltammetry
154
AC Impedance Measurement While Maintaining DC Bias to the Sensor
157
DMA Controller
163
DMA Features
163
DMA Overview
163
DMA Analog die
163
DMA Architectural Concepts
164
DMA Operating Modes
164
Channel Control Data Structure
164
Source Data End Pointer
165
Destination Data End Pointer
165
Control Data Configuration
166
DMA Priority
167
DMA Transfer Types
167
DMA Interrupts and Exceptions
173
Endian Operation
174
DMA Channel Enable and Disable
174
DMA Master Enable
175
Power-Down Considerations
175
Register Summary: DMA
176
Register Details: DMA
177
Status Register
177
Configuration Register
177
Channel Primary Control Data Base Pointer Register
177
Channel Alternate Control Data Base Pointer Register
177
Channel Software Request Register
178
Channel Request Mask Set Register
178
Channel Request Mask Clear Register
178
Channel Enable Set Register
179
Channel Enable Clear Register
179
Channel Primary Alternate Set Register
179
Channel Primary Alternate Clear Register
180
Channel Priority Set Register
180
Channel Priority Clear Register
180
Bus Error Clear Register
181
Per Channel Bus Error Register
181
Per Channel Invalid Descriptor Clear Register
181
Channel Bytes Swap Enable Set Register
182
Channel Bytes Swap Enable Clear Register
182
Channel Source Address Decrement Enable Set Register
182
Channel Source Address Decrement Enable Clear Register
183
Channel Destination Address Decrement Enable Set Register
183
Channel Destination Address Decrement Enable Clear Register
183
FIFO Configuration Register
184
Data FIFO Read Register
184
Flash Controller
185
Flash Controller Features
185
Flash Controller Overview
185
Supported Commands
185
Protection and Integrity Features
185
Flash Controller Operation
185
Flash Memory Structure
186
Flash Access
188
Reading Flash
188
Erasing Flash
188
Writing Flash
188
Keyhole Writes
189
Burst Writes
189
DMA Writes
190
Protection and Integrity
190
Key Register
192
Clock and Timings
193
Flash Operating Modes
194
Register Summary: Flash Cache Controller (FLCC)
195
Register Details: Flash Cache Controller (FLCC)
196
Status Register
196
Interrupt Enable Register
198
Command Register
199
Write Address Register
200
Write Lower Data Register
200
Write Upper Data Register
200
Lower Page Address Register
200
Upper Page Address Register
201
Key Register
201
Write Abort Address Register
201
Write Protection Register
201
Signature Register
202
User Configuration Register
202
IRQ Abort Enable (Lower Bits) Register
203
IRQ Abort Enable (Upper Bits) Register
203
ECC Configuration Register
203
ECC Status (Address) Register
203
Analog Devices Flash Security Register
204
Sram
205
SRAM Features
205
Instruction Vs. Data SRAM
206
SRAM Retention in Hibernate Mode
206
SRAM Initialization
206
Cache
208
Initialization in Cache and Instruction SRAM
208
Programming Guidelines
208
Register Summary: Cache (FLCC_CACHE)
209
Register Details: Cache (FLCC_CACHE)
210
Cache Status Register
210
Cache Setup Register
210
Cache Key Register
210
Silicon Identification
211
Register Summary: System (Digital Die)
212
Register Details: System (Digital Die)
213
Analog Devices Identification (Digital Die) Register
213
Chip Identifier (Digital Die) Register
213
Serial Wire Debug Enable Register
213
Analog Devices Identification (Analog Die) Register
213
Chip Identification (Analog Die) Register
213
16-Bit Scratch Register to Test Interdie Communications Register
213
Digital Inputs and Outputs
214
Digital Inputs and Outputs Features
214
Digital Inputs and Outputs Overview
214
Digital Inputs and Outputs Operation
215
Interrupts
215
Digital die Port Mux
217
AFE die Digital Port Mux
217
Register Summary: Digital Inputs and Outputs
218
Register Details: Digital Inputs and Outputs
220
GPIO Port Configuration Registers
220
GPIO Port Output Enable Registers
220
GPIO Port Input/Output Pull-Up Enable Registers
220
GPIO Port Input Path Enable Registers
221
GPIO Port Registered Data Input Registers
221
GPIO Port Data Output Registers
221
GPIO Port Data Output Set Registers
221
GPIO Port Data Output Clear Registers
222
GPIO Port Pin Toggle Registers
222
GPIO Port Interrupt Polarity Registers
222
GPIO Port Interrupt a Enable Registers
222
GPIO Port Interrupt B Enable Registers
223
GPIO Port Interrupt Status Registers
223
GPIO Port Drive Strength Select Registers
223
AFE GPIO Port Configuration Register
223
AFE GPIO Port Output Enable Register
224
AFE GPIO Port Output Pull-Up and Pull-Down Enable Register
224
AFE GPIO Port Input Path Enable Register
224
AFE GPIO Port Registered Data Input
224
AFE GPIO Port Data Output Register
224
AFE GPIO Port Data Output Set Register
225
AFE GPIO Port Data Output Clear Register
225
AFE GPIO Port Pin Toggle Register
225
I 2 C Serial Interface
226
I 2 C Features
226
I 2 C Overview
226
I 2 C Operation
226
I 2 C Operating Modes
228
Register Summary: I C
231
Register Details: I
232
Master Control Register
232
Master Status Register
232
Master Receive Data Register
233
Master Transmit Data Register
234
Master Receive Data Count Register
234
Master Current Receive Data Count Register
234
First Master Address Byte Register
234
Second Master Address Byte Register
234
Serial Clock Period Divisor Register
235
Slave Control Register
235
Slave I 2 C Status, Error, and IRQ Register
236
Slave Receive Register
237
Slave Transmit Register
237
Hardware General Call ID Register
237
First Slave Address Device ID Register
237
Second Slave Address Device ID Register
238
Third Slave Address Device ID Register
238
Fourth Slave Address Device ID Register
238
Master and Slave FIFO Status Register
238
Master and Slave Shared Control Register
239
Automatic Stretch Control for Master and Slave Mode Register
239
Serial Peripheral Interfaces
241
SPI Features
241
SPI Overview
241
SPI Operation
241
SPI Transfer Initiation
242
SPI Interrupts
244
SPI Wire-Or'ed Mode
245
SPI CSERR Condition
245
Spi Dma
245
SPI and Power-Down Modes
246
Register Summary: SPI0/SPI1
247
Register Details: SPI0/SPI1
248
Status Registers
248
Receive Registers
249
Transmit Registers
249
Baud Rate Selection Registers
249
Configuration Registers
250
Interrupt Configuration Registers
251
Transfer Byte Count Registers
252
DMA Enable Registers
252
FIFO Status Registers
253
Read Control Registers
254
Flow Control Registers
255
Wait Timer for Flow Control Registers
255
Chip Select Override Registers
255
UART Serial Interface
256
UART Overview
256
UART Features
256
UART Operation
256
Register Summary: UART
259
Register Details: UART
260
Transmit Holding Register
260
Receive Buffer Register
260
Interrupt Enable Register
260
Interrupt Identification Register
261
Line Control Register
261
Modem Control Register
262
Line Status Register
262
Modem Status Register
263
Scratch Buffer Register
263
FIFO Control Register
263
Fractional Baud Rate Register
264
Baud Rate Divider Register
264
Second Line Control Register
264
UART Control Register
265
Receive FIFO Count Register
265
Transmit FIFO Count Register
265
RS485 Half-Duplex Control Register
265
Autobaud Control Register
266
Autobaud Status (Low) Register
266
Autobaud Status (High) Register
266
Digital die General-Purpose Timers
267
Digital die General-Purpose Timers Features
267
General-Purpose Timers Overview
267
General-Purpose Timer Operations
267
Register Summary: General-Purpose Timers
270
Register Details: General-Purpose Timers
271
16-Bit Synchronous Load Value Registers
271
16-Bit Timer Synchronous Value Registers
271
Control Registers
271
Clear Interrupt Registers
272
Capture Registers
272
16-Bit Asynchronous Load Value Registers
273
16-Bit Timer Asynchronous Value Registers
273
Status Registers
273
Analog die General-Purpose Timers
274
Analog die General-Purpose Timers Features
274
Afe Pwm
274
Register Summary: Analog die General-Purpose Timers
275
Register Details: Analog die General-Purpose Timers
276
16-Bit Load Value Register
276
16-Bit Timer Value Register
276
Control Register
276
Clear Interrupt Register
277
16-Bit Load Value, Asynchronous Register
277
16-Bit Timer Value, Asynchronous Register
277
Status Register
278
PWM Control Register
278
PWM Match Value Register
278
Interrupt Enable Register
279
16-Bit Load Value Register
279
16-Bit Timer Value Register
279
Control Register
279
Clear Interrupt Register
280
16-Bit Load Value, Asynchronous Register
280
16-Bit Timer Value, Asynchronous Register
281
Status Register
281
PWM Control Register
281
PWM Match Value Register
281
AFE Watchdog Timer
282
Watchdog Timer Features and Block Diagram
282
Watchdog Timer Operation
282
Windowed Watchdog Feature
282
Interrupt Mode
282
Register Summary: AFE Watchdog Timer
283
Register Details: AFE Watchdog Timer
284
Watchdog Timer Load Value Register
284
Current Count Value Register
284
Watchdog Timer Control Register
284
Refresh Watchdog Register
285
Timer Status Register
285
Minimum Load Value Register
286
Digital die Wake-Up Timer
287
Overview
287
Features
287
Regular and Periodic Modulo 60 Interrupts
287
Timer Matching Alarm Value Interrupts
287
WUT Functional Description
287
WUT Operating Modes
288
WUT Recommendations: Clock and Power
288
Register Summary: Digital die Wake-Up Timer
290
Register Details: Digital die Wake-Up Timer
291
Control 0 Register
291
Status 0 Register
292
Status 1 Register
294
Count 0 Register
295
Count 1 Register
295
Alarm 0 Register
296
Alarm 1 Register
296
Gateway Register
296
Control 1 Register
297
Status 2 Register
298
Snapshot 0 Register
299
Snapshot 1 Register
300
Snapshot 2 Register
300
Modulo Register
300
Count 2 Register
301
Alarm 2 Register
301
Status 6 Register
302
Cyclic Redundancy Check
303
CRC Features
303
CRC Functional Description
303
CRC Data Transfer
306
CRC Interrupts and Exceptions
306
CRC Programming Model
306
Register Summary: CRC
308
Register Details: CRC
309
CRC Control Register
309
Input Data Word Register
309
CRC Result Register
309
Programmable CRC Polynomial Register
309
Input Data Bits Register
310
Input Data Byte Register
310
Hardware Design Considerations
311
Typical System Configuration
311
Serial Wire Debug Interface
312

Analog Devices ADuCM355 Diagrams (2 pages)

Brand: Analog Devices | Category: Computer Hardware | Size: 0 MB

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