Analog Devices ADuCM356 Reference Manual page 141

Reference Manual
AFE INTERRUPTS
Table 178. Bit Descriptions for INTCFLAG0 and INTCFLAG1 Registers (Continued)
Bits Bit Name Settings
8 Reserved
7 FLAG7
6 FLAG6
5 FLAG5
4 FLAG4
3 FLAG3
2 FLAG2
1 FLAG1
0 FLAG0
Analog Generation Interrupt Register
Address: 0x400C209C, Reset: 0x00000010, Name: AFEGENINTSTA
The AFEGENINTSTA register provides custom interrupt generation. Writing to this register is only possible using the sequencer.
Table 179. Bit Descriptions for AFEGENINTSTA Register
Bits Bit Name Description
[31:4] Reserved Reserved.
3 CUSTOMINT3 General-Purpose Custom Interrupt 3. Set this bit manually using the sequencer program. Write 1 to this bit to trigger
an interrupt.
2 CUSTOMINT2 General-Purpose Custom Interrupt 2. Set this bit manually using the sequencer program. Write 1 to this bit to trigger
an interrupt.
1 CUSTOMINT1 General-Purpose Custom Interrupt 1. Set this bit manually using the sequencer program. Write 1 to this bit to trigger
an interrupt.
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Description
0 Interrupt not asserted.
1 Interrupt asserted.
Reserved.
Mean IRQ Status.
0 Interrupt not asserted.
1 Interrupt asserted.
ADC Delta Fail IRQ Status. When this bit is set, it indicates that the difference between two consecutive
ADC results is greater than the value specified by the ADCDELTA register. If this bit is clear, it indicates
that no difference between two consecutive ADC values greater than the limit is detected since the last
time this bit was cleared.
0 Interrupt not asserted.
1 Interrupt asserted.
ADC Maximum Fail IRQ Status. When this bit is set, it indicates that an ADC result is above the
maximum value specified by the ADCMAX register. If this bit is clear, it indicates that no ADC value
above the maximum is detected.
0 Interrupt not asserted.
1 Interrupt asserted.
ADC Minimum Fail IRQ Status. When this bit is set, it indicates that an ADC result is below the minimum
value as specified by the ADCMIN register. If this bit is clear, it indicates that no ADC value below the
limit is detected since the last time this bit was cleared.
0 Interrupt not asserted.
1 Interrupt asserted.
Temperature Result IRQ Status.
0 Interrupt not asserted.
1 Interrupt asserted.
Sinc2 Filter Result Ready IRQ Status.
0 Interrupt not asserted.
1 Interrupt asserted.
DFT Result IRQ Status.
0 Interrupt not asserted.
1 Interrupt asserted.
ADC Result IRQ Status.
0 Interrupt not asserted.
1 Interrupt asserted.
ADuCM356
Reset Access
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
Reset Access
0x1 R
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
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