Analog Devices ADuCM356 Reference Manual page 166

Reference Manual
DMA CONTROLLER
Table 194. CHNL_CFG for Primary Data Structure in Memory Scatter Gather Mode, CHNL_CFG, Bits[2:0] = 100
Bit(s) Name
[31:30] DST_INC
[29:28] Reserved
[27:26] SRC_INC
[25:24] SRC_SIZE
[23:18] Reserved
[17:14] R_POWER
[13:4] N_MINUS_1
3 Reserved
[2:0] CYCLE_CTRL
Peripheral Scatter Gather (CHNL_CFG,
Bits[2:0] = 110 or 111)
In peripheral scatter gather mode, the controller must be configured
to use both the primary and alternate data structures. The controller
uses the primary data structure to program the control structure of
the alternate data structure. The alternate data structure is used for
actual data transfers, and each transfer takes place using the alter-
nate data structure with a basic DMA transfer. The controller does
not arbitrate after every primary transfer. The peripheral scatter
gather mode is used when there are multiple peripheral to memory
DMA tasks to be performed. The Cortex-M3 can configure all of the
tasks simultaneously and does not need to intervene in between
each task.
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Description
Set to 10, configures the controller to use word increments for the address.
Undefined. Write as 0.
Set to 10, configures the controller to use word increments for the address.
Set to 10, configures the controller to use word transfers.
Undefined. Write as 0.
Set to 0010, indicates that the DMA controller is ready to perform four transfers.
Configures the controller to perform N DMA transfers, where N is a multiple of four.
Undefined. Write as 0.
Set to 100, configures the controller to perform a memory scatter gather DMA cycle.
Figure 46. Memory Scatter Gather DMA Transfer
The peripheral scatter gather mode is very similar to the memory
scatter gather mode except for the arbitration and request require-
ments. The MCU generates the corresponding DMA_DONE chan-
nel interrupt in the NVIC when the entire scatter gather transaction
completes using a basic cycle.
In peripheral scatter gather mode, the controller receives an initial
request from a peripheral and then performs four DMA transfers
using the primary data structure to program the alternate control
data structure. The controller then immediately starts a DMA cycle
using the alternate data structure without rearbitrating.
After this cycle completes, the controller rearbitrates, and if it
receives a request from the peripheral that has the highest priori-
ty, the controller performs another four DMA transfers using the
primary data structure. The controller then immediately starts a
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