Register Summary: Spi0/Spi1 - Analog Devices ADuCM356 Reference Manual

Reference Manual

REGISTER SUMMARY: SPI0/SPI1

Table 305. SPI Register Summary
Address Name
0x40004000 SPI0_STAT
0x40004004 SPI0_RX
0x40004008 SPI0_TX
0x4000400C SPI0_DIV
0x40004010 SPI0_CTL
0x40004014 SPI0_IEN
0x40004018 SPI0_CNT
0x4000401C SPI0_DMA
0x40004020 SPI0_FIFO_STAT
0x40004024 SPI0_RD_CTL
0x40004028 SPI0_FLOW_CTL
0x4000402C SPI0_WAIT_TMR
0x40004034 SPI0_CS_OVERRIDE
0x40024000 SPI1_STAT
0x40024004 SPI1_RX
0x40024008 SPI1_TX
0x4002400C SPI1_DIV
0x40024010 SPI1_CTL
0x40024014 SPI1_IEN
0x40024018 SPI1_CNT
0x4002401C SPI1_DMA
0x40024020 SPI1_FIFO_STAT
0x40024024 SPI1_RD_CTL
0x40024028 SPI1_FLOW_CTL
0x4002402C SPI1_WAIT_TMR
0x40024034 SPI1_CS_OVERRIDE
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Description
Status
Receive
Transmit
Baud rate selection
Configuration
Interrupt configuration
Transfer byte count
DMA enable
FIFO status
Read control
Flow control
Wait timer for flow control
Chip select override
Status
Receive
Transmit
Baud rate selection
Configuration
Interrupt configuration
Transfer byte count
DMA enable
FIFO status
Read control
Flow control
Wait timer for flow control
Chip select override
ADuCM356
Reset Access
0x0800 R
0x0000 R
0x0000 W
0x0000 R/W
0x0000 R/W
0x0000 R/W
0x0000 R/W
0x0000 R/W
0x0000 R
0x0000 R/W
0x0000 R/W
0x0000 R/W
0x0000 R/W
0x0800 R
0x0000 R
0x0000 W
0x0000 R/W
0x0000 R/W
0x0000 R/W
0x0000 R/W
0x0000 R/W
0x0000 R
0x0000 R/W
0x0000 R/W
0x0000 R/W
0x0000 R/W
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