Recommended Configuration In Hibernate Mode; High-Speed Dac Filter Options; High-Speed Dac Output Attenuation Options - Analog Devices ADuCM356 Reference Manual

Reference Manual
HIGH-SPEED DAC CIRCUITS
High-Power Mode
When configuring the high-speed DAC for high-power mode, take
note of the following requirements and features:
Increases the bandwidth supported by the high-speed DAC
►
amplifiers.
Set PMBW, Bit 0 = 1. Power consumption is increased, but the
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output signal bandwidth increases to a maximum of 200 kHz.
In this mode, the system clock to the DAC and the ADC must be
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set to 32 MHz.
Ensure CLKSEL, Bits[1:0] selects a 32 MHz clock source. For
►
example, an internal high-speed oscillator is selected if CLKSEL,
Bits[1:0] = 00. Ensure that the system clock divide ratio is 1
(CLKCON0, Bits[5:0] = 0 or 1).
If the internal high-speed oscillator is selected as the system
►
clock source, ensure that the 32 MHz option is selected. Clear
HPOSCCON, Bit 2 = 0.
Hibernate Mode
When configuring the high-speed DAC for hibernate mode, take
note of the following requirements and features:
When the ADuCM356 enters hibernate mode, the clocks to the
►
high-speed DAC circuits are clock gated to save power.
When the ADuCM356 is in active mode but the high-speed DAC
►
is not required, disable the high-speed DAC circuits to save
power. To do this, clear Bit 20, Bit 14, Bit 10, Bit 9, and Bit 6
in the AFECON register. Leave Bit 5 set if the ADC is in use,
because Bit 5 controls the high-power reference source.
RECOMMENDED CONFIGURATION IN
HIBERNATE MODE
To minimize leakage on the switches connected to the excitation
amplifier P and N nodes and to minimize leakage on the high-speed
TIA, tie the switches to the internal 1.8 V LDO regulator generated
voltage, as follows:
Close the PL and PL2 switches. PSWFULLCON, Bits[14:13] =
►
11.
Close the NL and NL2 switches. NSWFULLCON, Bits[11:10] =
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11.
In hibernate mode, assume that only the DC bias voltage from the
low-power amplifiers is required for the sensor.

HIGH-SPEED DAC FILTER OPTIONS

The high-speed DAC has a configurable reconstruction filter on its
output stage. It is important that this filter is configured appropriately
depending on the output signal frequency of the DAC. PMBW,
Bits[3:2] configure the 3 dB cutoff frequency of the filters. Ensure
that the cutoff frequency is higher than the required DAC output
frequency. The output filter cutoff frequency details are as follows:
analog.com
PMBW, Bits[3:2] = 01 for optimal performance if the DAC output
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signal frequency is <80 kHz.
PMBW, Bits[3:2] = 10 for optimal performance if the DAC output
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signal frequency is <100 kHz.
PMBW, Bits[3:2] = 11 for optimal performance if the DAC output
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signal frequency is <250 kHz.
HIGH-SPEED DAC OUTPUT ATTENUATION
OPTIONS
Scaling options for the high-speed DAC output exist to modify the
output signal amplitude to the sensor. The output of the 12-bit DAC
string before any attenuation or gain is approximately ±300 mV. At
the DAC output, there is a 1 or 0.2 gain stage that is controlled
by HSDACCON, Bit 0. At the PGA stage, there is a 2 or 0.25 gain
option that is controlled by HSDACCON, Bit 12.
It is recommended to only use the maximum and minimum overall
gain options with the lowest DAC code of 0x200 and maximum
DAC code of 0xE00. The characterized DAC output ranges are as
follows:
HSDACCON, Bit 12 = 0 and HSDACCON, Bit 0 = 0. The overall
►
gain is 2. This setting gives a full-scale voltage of approximately
±607 mV to the sensor for HSDACDAT Code 0x200 to Code
0xE00.
HSDACCON, Bit 12 = 1 and HSDACCON, Bit 0 = 1. This setting
►
gives a full-scale voltage of approximately ±15.1 mV to the
sensor for HSDACDAT Code 0x200 to Code 0xE00.
ADuCM356
Rev. A | 105 of 312