Spi Cserr Condition; Spi Dma - Analog Devices ADuCM356 Reference Manual

Reference Manual
SERIAL PERIPHERAL INTERFACES
resistor is required when this feature is selected. The wire-OR bit
(SPIx_CTL, Bit 4) controls the pad enable outputs for the data lines.

SPI CSERR CONDITION

The CSERR bit (SPIx_STAT, Bit 12) indicates if an erroneous deas-
sertion of the CS signal has been detected before the completion
of all eight SCLK cycles. This bit generates an interrupt and is
available in all modes of operation: target, initiator, and during DMA
transfers. If an interrupt generated by SPIx_STAT, Bit 12 occurs,
SPIx_CTL, Bit 0 must be disabled and restarted to enable a clean
recovery to ensure that subsequent transfers are error free.

SPI DMA

Two DMA channels are dedicated to transmit and receive. The
SPI DMA channels must be configured in the microDMA controller
of the Arm Cortex-M3 processor. It is possible to enable a DMA
request on one or two channels at the same time by setting the
DMA request bits for receive or transmit in the SPIx_DMA register.
If only the DMA transmit request (SPIx_DMA, Bit 1) is enabled, the
receive FIFO overflows during an SPI transfer, unless the received
data is read by user code, in which case an overflow interrupt is
generated. To avoid generating overflow interrupts, set the receive
FIFO flush bit, or disable the SPI interrupt in the NVIC. If only the
DMA receive request (SPIx_DMA, Bit 2) is enabled, the transmit
FIFO is underrun. To avoid an underrun interrupt, the SPI interrupt
must be disabled.
The SPI transmit (SPIx_STAT, Bit 5) and SPI receive (SPIx_STAT,
Bit 6) interrupts are not generated when using DMA. The SPI trans-
mit underflow (SPIx_STAT, Bit 4) and receive overflow (SPIx_STAT,
Bit 7) interrupts are generated when using the microDMA controller.
SPIx_IEN, Bits[2:0] are not used in transmit mode and must be set
to 0b000 in receive mode.
SPIx_DMA, Bit 0 controls the start of a DMA transfer. DMA re-
quests are only generated when SPIx_DMA, Bit 0 = 1. At the end
of a DMA transfer, this bit must be cleared to prevent extra DMA
requests to the microDMA controller. The data still present in the
transmit FIFO is transmitted if in transmit mode. All DMA data
transfers are 16-bit transfers. Program the DMA accordingly. For
example, if 16 bytes of data are to be transferred over the SPI,
program the DMA to perform eight half word (16-bit) transfers. If 17
bytes are to be transferred, nine half word transfers are required.
In DMA mode, the transmit and receive FIFOs are two bytes wide.
Bits[7:0] are first accessed by the SPI, followed by Bits[15:8]. This
is irrespective of count or SPIx_CTL, Bit 5 settings.
For example, if SPI_CNT, Bits[13:0] = 3, the order of transmission
and reception is Byte 1, Byte 0 followed by Byte 3 (ignore), and
Byte 2. SPI_CTL, Bit 5 does not affect the FIFO access order
in DMA mode. SPI_CTL, Bit 5 only affects how each byte is
transferred over SPI.
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DMA Initiator Transmit Configuration
The DMA SPI transmit channel must be configured. Configure the
NVIC to enable DMA transmit initiator interrupts.
All DMA transfers are 16-bit transfers. When all data present in the
DMA buffer is transmitted, the DMA generates an interrupt. User
code must disable the DMA request. Data is still in the transmit
FIFO because the DMA request is generated each time there is
free space in the transmit FIFO to keep the FIFO full. User code
can check how many bytes are still present in the FIFO in the
SPIx_FIFO_STAT register. The SPI block must be configured as
follows:
SPI_DIV = SPI_SERIAL_FREQ; //configures seri►
al clock frequency.
SPI_CTL = 0x1043;
itiator mode and transmit mode, receive FIFO
//flush enabled.
SPI_CNT.VALUE = NUM_BYTES_TO transfer; //sets
the number of bytes to transfer. SPI_DMA =
0x1;
//(optional) enables FIFO to accept 16-bit
//core data writes.
SPI_TX = 0xXXXX;
16-bit core writes can be performed
//to preload FIFO.
SPI_DMA = 0x3; //enable DMA mode, enable
transmit DMA request.
DMA Initiator Receive Configuration
The SPIx_CNT register is available in DMA receive initiator mode
only. This register sets the number of receive bytes required by the
SPI initiator or the number of clocks that the initiator must generate.
When the required number of bytes are received, no more transfers
are initiated. To initiate a DMA initiator receive transfer, complete a
dummy read by user code. Add this dummy read to the SPIx_CNT
number.
The counter counting the bytes as they are received is reset either
when SPI is disabled in SPIx_CTL, Bit 0 or when the SPIx_CNT
register is modified by user code.
Performing SPI DMA Initiator Receive
The DMA SPI receive channel must be configured. The NVIC must
be configured to enable DMA receive initiator interrupts. The SPI
block must be configured as follows:
SPI_DIV = SPI_SERIAL_FREQ; //configures serial
clock frequency.
SPI_CTL = 0x2003;
mode and
//receive mode, 1 byte transfer.
SPI_DMA = 0x5;
ADuCM356
//enables SPI in in►
//(optional) up to four
//enable SPI in initiator
//enable DMA mode, en►
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