The logging target is 512 bits, but the time information (80 bits) is given in the logging part. Output 432 bits for the logging target output from the user

circuit. Set unused bits to 0 fixed output.

For details on assigning logging targets output from the sample circuit, refer to the following.

Page 714 Logging Data Bit Assignment

For user circuit data sampling pulse, D/A conversion value enable (E0 to E2), and user sampling pulse, do not set them to less than the minimum

value described in  Page 193 Timing generator (tg2_top). Otherwise, it will not work properly. The constraint conditions are shown below.

• H-significant 1-pulse signal

• 1b

• The minimum pulse interval is the same as  Page 193 Timing generator (tg2_top).

The user circuit data sampling pulse has the same constraints as the analog input/output circuit board for the data sampling timing.

D/A conversion enable (E0 to E2) has the same constraints as the analog input/output circuit board for the data update timing.

The user sampling pulse has the same constraints as the logging cycle timing pulse.

For details, refer to the following.

Page 231 Analog input/output circuit board (input)

Page 220 Logging control (output)

Operation when constraint conditions are not met is shown in  Page 236 Operation when pulse interval constraint is violated.

Set the width from Enable (1) of D/A conversion value enable (E0) to Enable(0) of LDAC output CH0-1 (E0) to 5.7s or more. Also, set the effective

period of LDAC output CH0-1 (E0) to 300ns or more.

Operation when constraint conditions are not met is shown in  Page 236 Operation when LDAC constraint is violated.

Set all outputs to the outside of the user circuit to flip-flop output.

Use the system clock (clk100m). When generating and using a clock in the user circuit, synchronize the output signal with the system clock (clk100m).

Asynchronous processing is not implemented in the standard circuit.

Start the operation of the user circuit after activating "Internal operation start/stop".

Since the module specific circuit of the standard circuit does not operate while "Internal operation start/stop" is stopped, the signal from the user circuit

is ignored. The reset sequence is shown in  Page 237 Reset sequence.

When the DC input/output circuit board is selected, the FPGA loads the lower ([7:0]) and upper ([15:8]) of the digital signal ([15:0]) in time division.

Note that there is a 100ns lag between the upper and lower parts of the digital signal loading timing.

When the differential input/output circuit board is connected, if "Internal operation start/stop" is set to Stop, the output value of the digital signal ([7:0])

that is output to the outside of the FPGA can be specified. Set the output from the user circuit and "Differential output HOLD/CLEAR" according to the

device to be connected externally, and output the signal to the outside of the FPGA.

Example: When the initial value of the externally connected device is 1b

• Set the output of the user circuit part to 1b.

• Set "Differential output HOLD/CLEAR" to 1b (CLEAR (1b fixed)).

Use the logging control part in the fixed automatic transfer mode by F/W. When designing the user circuit part, output the logging start signal (user

circuit part) according to Logging control trigger signal (re_rs_lgdw_ctrl_3_clk100m_reg).

11 FPGA INTERNAL CIRCUIT

11.4 User Circuit Block

235

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