Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 549

D/A conversion timing selection
■Address
Name
D/A conversion timing selection (aoport_da_cyc_sel)
■Description
Selects the D/A conversion timing of DAC.
b15 b14 b13 b12
0 (fixed)
(1) D/A conversion timing selection (E0)
*1
• 1: User circuit output
*2
• 0: Data update timing
(2) D/A conversion timing selection (E1)
*1
• 1: User circuit output
*2
• 0: Data update timing
(3) D/A conversion timing selection (E2)
*1
• 1: User circuit output
*2
• 0: Data update timing
*1 Perform the D/A conversion with D/A conversion value enable (E) (uc_ioeandat_en_clk100m_reg) from the user circuit part.
*2 D/A conversion is performed at the cycle set by the data update timing.
■FPGA initial value
0
■Firmware initial value
0
■Reset cause
Reset
■Precautions and restrictions
• When a DC I/O circuit board or Differential I/O circuit board is connected to E, the settings are disabled.
• If data update timing (0) is set, set the following for each circuit board.
Item
D/A conversion value selection (aoport_da_data_sel)
DAC LDAC signal selection (aoport_da_ldac_sel)
• When setting the user circuit output (1), set the following for each circuit board.
Item
D/A conversion value selection (aoport_da_data_sel)
DAC LDAC signal selection (aoport_da_ldac_sel)
b11 b10 b9 b8 b7 b6 b5 b4
Description
Register setting value
Fixed to Low
Description
User circuit output
User circuit output
FPGA register address
1000_7004H
b3 b2 b1 b0
(3) (2) (1)
APPX
547
Appendix 4 FPGA register
A