Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 666

Cc-link ie tsn fpga module
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Connec-
Ter-
Exter-
tion cir-
minal
nal ter-
cuit
num-
minal
board
ber
name
DC I/O
B25
IOB2_X1
circuit
board
Differential
I/O circuit
board
DC I/O
B24
IOB2_X2
circuit
board
Differential
I/O circuit
board
DC I/O
C25
IOB2_X3
circuit
board
Differential
I/O circuit
board
DC I/O
D25
IOB2_X4
circuit
board
Differential
I/O circuit
board
DC I/O
D22
IOB2_X5
circuit
board
Differential
I/O circuit
board
DC I/O
E25
IOB2_X6
circuit
board
Differential
I/O circuit
board
DC I/O
E24
IOB2_X7
circuit
board
Differential
I/O circuit
board
DC I/O
D26
IOB2_X
circuit
OEL0
board
Differential
I/O circuit
board
DC I/O
E26
IOB2_X
circuit
OEL1
board
Differential
I/O circuit
board
APPX
664
Appendix 6 A List of FPGA External Terminals
Each
Func-
I/O di-
circuit
tions
rec-
board
tion
func-
tion ter-
minal
name
IOB2_X[1
DC input
Input
]
[1]
IOB2_DI4
Differential
22[1]
(RS-422)
input [1]
IOB2_X[2
DC input
Input
]
[2]
IOB2_DI4
Differential
22[2]
(RS-422)
input [2]
IOB2_X[3
DC input
Input
]
[3]
IOB2_DI4
Differential
22[3]
(RS-422)
input [3]
IOB2_X[4
DC input
Input
]
[4]
IOB2_DI4
Differential
22[4]
(RS-422)
input [4]
IOB2_X[5
DC input
Input
]
[5]
IOB2_DI4
Differential
22[5]
(RS-422)
input [5]
IOB2_X[6
DC input
Input
]
[6]
IOB2_DI4
Differential
22[6]
(RS-422)
input [6]
IOB2_X[7
DC input
Input
]
[7]
IOB2_DI4
Differential
22[7]
(RS-422)
input [7]
IOB2_XO
DC input
Output
EL[0]
output
enable [0]
IOB2_DI
Differential
O485_EN
(RS-485) I/
O direction
IOB2_XO
DC input
Input/
EL[1]
output
output
enable [1]
IOB2_DI
Differential
O485_I
(RS-485)
input
I/O di-
I/O
I/O
Logic
rec-
type
volt-
tion
age
for
each
cir-
cuit
board
Input
3.3-V
3.3V
LVCM
OS
Input
Input
3.3-V
3.3V
LVCM
OS
Input
Input
3.3-V
3.3V
LVCM
OS
Input
Input
3.3-V
3.3V
LVCM
OS
Input
Input
3.3-V
3.3V
LVCM
OS
Input
Input
3.3-V
3.3V
LVCM
OS
Input
Input
3.3-V
3.3V
LVCM
OS
Input
Output
3.3-V
3.3V
Negative
LVCM
OS
Output
Positive/
negative
Output
3.3-V
3.3V
Negative
LVCM
OS
Input
PU/
Initial state
Operating
PD in
frequency
Re-
After
FPGA
set-
reset
ting
re-
lease
PU
H
L
20MHz
4.17MHz
PU
L
L
20MHz
4.17MHz
PU
H
L
20MHz
4.17MHz
PU
L
L
20MHz
4.17MHz
PU
H
L
20MHz
4.17MHz
PU
H
L
20MHz
4.17MHz
PU
H
L
20MHz
4.17MHz
PU
L
H
20MHz
L
Asynchronous
PU
H
H
20MHz
L
10MHz

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