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■Function List
Function
Description
Read data output
Outputs various statuses to check the internal status of the user circuit.
Also, it selects and connects the FPGA internal status, "Write data (transient area)", and "Write data (cyclic area)" by setting "Test
mode setting".
For details, refer to the following.
Page 592 Test mode setting
Always read register output
Connects the always write register 0 to C15 to always read register 0 to 15 in one flip-flop level (clk100m). Connections for
exceptions are shown below.
Always write register 14[0]: Logging control violation flag rising edge clear
Always write register 14[1]: Logging control violation flag falling edge clear
Always read register 14[0]: Logging control violation flag rising edge
Always read register 14[1]: Logging control violation flag falling edge
Error signal output
"User circuit part error signal generation [0]" is output in one flip-flop level (clk100m).
Digital output control
Selects the signal from the pulse output part or digital control part and outputs it as a digital signal.
Also, depending on the setting value of "Digital output HOLD/CLEAR", "Microcomputer system error notification" is set to Enable
(1) and the output value is HOLD/CLEAR.
Digital input/output control
"Digital input/output control input/output control register (B0) [3:2]" is output in one flip-flop level (clk100m).
Also, depending on the setting value of "Digital output HOLD/CLEAR", "Microcomputer system error notification" is set to Enable
(1) and the output value is HOLD/CLEAR.
General-purpose output
Outputs general-purpose input (cpu_intpl_in). (Outputs in one flip-flop level (clk100m))
Data sampling pulse output
Outputs the signal that detected the rising edge of "Analog control data sampling pulse generation
(re_rs_usr_wreg_1c8_clk100m_reg)".
ADC conversion enable
Sets when A/D conversion value enable (E0), (E1), (E2) from extension module (E0, E1, E2) is set to Enable (1), and resets
status
when internal operation start/stop is Stop (1). The set/reset signal is connected to the read data.
A/D conversion value
Holds the maximum and minimum A/D conversion values of the extension module (E0, E1, E2). The maximum initial value is set
maximum/minimum hold
to 8000H and the minimum initial value is set to 7FFFH, and when "A/D conversion value enable" is set to Enable (1), they are
compared with the A/D conversion value and held.
Also, at the rising edge of "Analog control A/D conversion value maximum/minimum current value update", "A/D conversion
value maximum/minimum" is updated to the current value. When this happens, priority is given in descending order of analog
control A/D conversion value maximum/minimum current value update and analog input enable.
■Terminal list
Signal name
clk100m
usr_rst_n
dig_iob0_y_clk100m_reg[15:0]
dig_iob1_y_clk100m_reg[15:0]
dig_iob2_y_clk100m_reg[15:0]
dig_ioe0_y_clk100m_reg[15:0]
dig_ioe1_y_clk100m_reg[15:0]
dig_ioe2_y_clk100m_reg[15:0]
dig_iob0_dio485_o_clk100m_reg
dig_iob1_dio485_o_clk100m_reg
dig_iob2_dio485_o_clk100m_reg
dig_ioe0_dio485_o_clk100m_reg
dig_ioe1_dio485_o_clk100m_reg
dig_ioe2_dio485_o_clk100m_reg
I/O
Logic
Description
I
System clock
I
L
Reset for user circuit (the AND between
reset and internal operation start/stop)
I
Digital output signal (B0 after digital
control)
I
Digital output signal (B1 after digital
control)
I
Digital output signal (B2 after digital
control)
I
Digital output signal (E0 after digital
control)
I
Digital output signal (E1 after digital
control)
I
Digital output signal (E2 after digital
control)
I
Digital output signal (digital input/output B0
after digital control)
I
Digital output signal (digital input/output B1
after digital control)
I
Digital output signal (digital input/output B2
after digital control)
I
Digital output signal (digital input/output E0
after digital control)
I
Digital output signal (digital input/output E1
after digital control)
I
Digital output signal (digital input/output E2
after digital control)
Connection
Initial
Pulse
destination
value
signal
cc2_top
uc2_top
1b
Digital control
0000H
part
Digital control
0000H
part
Digital control
0000H
part
Digital control
0000H
part
Digital control
0000H
part
Digital control
0000H
part
Digital control
0b
part
Digital control
0b
part
Digital control
0b
part
Digital control
0b
part
Digital control
0b
part
Digital control
0b
part
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
11
289
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Table of Contents
Troubleshooting
