Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 646

Connection destination
Block name Instance
name
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
APPX
644
Appendix 5 List of User Circuit Block Terminals
Terminal
signal Signal name
re_rs_usr_rreg_15 Read data 337
1_clk100m_reg
re_rs_usr_rreg_15 Read data 338
2_clk100m_reg
re_rs_usr_rreg_15 Read data 339
3_clk100m_reg
re_rs_usr_rreg_15 Read data 340
4_clk100m_reg
re_rs_usr_rreg_15 Read data 341
5_clk100m_reg
re_rs_usr_rreg_15 Read data 342
6_clk100m_reg
re_rs_usr_rreg_15 Read data 343
7_clk100m_reg
re_rs_usr_rreg_15 Read data 344
8_clk100m_reg
re_rs_usr_rreg_15 Read data 345
9_clk100m_reg
re_rs_usr_rreg_15 Read data 346
a_clk100m_reg
re_rs_usr_rreg_15 Read data 347
b_clk100m_reg
re_rs_usr_rreg_15 Read data 348
c_clk100m_reg
re_rs_usr_rreg_15 Read data 349
d_clk100m_reg
re_rs_usr_rreg_15 Read data 350
e_clk100m_reg
re_rs_usr_rreg_15f Read data 351
_clk100m_reg
re_rs_usr_rreg_16 Read data 352
0_clk100m_reg
re_rs_usr_rreg_16 Read data 353
1_clk100m_reg
re_rs_usr_rreg_16 Read data 354
2_clk100m_reg
re_rs_usr_rreg_16 Read data 355
3_clk100m_reg
re_rs_usr_rreg_16 Read data 356
4_clk100m_reg
re_rs_usr_rreg_16 Read data 357
5_clk100m_reg
re_rs_usr_rreg_16 Read data 358
6_clk100m_reg
re_rs_usr_rreg_16 Read data 359
7_clk100m_reg
re_rs_usr_rreg_16 Read data 360
8_clk100m_reg
re_rs_usr_rreg_16 Read data 361
9_clk100m_reg
re_rs_usr_rreg_16 Read data 362
a_clk100m_reg
re_rs_usr_rreg_16 Read data 363
b_clk100m_reg
re_rs_usr_rreg_16 Read data 364
c_clk100m_reg
re_rs_usr_rreg_16 Read data 365
d_clk100m_reg
Bit Input/ Polarity
width output

16 Output

16 Output

16 Output
16 Output 

16 Output

16 Output
16 Output 

16 Output

16 Output

16 Output

16 Output

16 Output
16 Output 

16 Output

16 Output

16 Output
16 Output 

16 Output

16 Output
16 Output 

16 Output

16 Output

16 Output

16 Output

16 Output
16 Output 

16 Output

16 Output

16 Output
Initial 1shot Sync clock
value
Feq

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m