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Analog output control part
: Applicable, : Not applicable
FPGA register address
Register name
1000_7000H
aoport_da_start
1000_7002H
aoport_da_data_sel
1000_7004H
aoport_da_cyc_sel
1000_7006H
aoport_da_ldac_sel
1000_7100H
aoport_dae0_0_data
1000_7102H
aoport_dae0_1_data
1000_7104H
aoport_dae1_0_data
1000_7106H
aoport_dae1_1_data
1000_7108H
aoport_dae2_0_data
1000_710AH
aoport_dae2_1_data
Logging part
: Applicable, : Not applicable
FPGA register address
Register name
1000_9000H
lgdw_ctrl
1000_9002H
lgdw_sts
1000_9004H
lgdw_sys_sts
1000_9006H
lgdw_flag_clr
1000_9008H
lgdw_area
1000_9030H
lgdw_clock_rddata1
1000_9032H
lgdw_clock_rddata2
1000_9034H
lgdw_clock_rddata3
1000_9036H
lgdw_clock_rddata4
1000_9038H
lgdw_clock_rddata5
1001_9000H
lgdw_triggered_lsample
1001_9002H
lgdw_triggered_usample
1001_9004H
lgdw_sample_lcount
1001_9006H
lgdw_sample_ucount
User circuit part
: Applicable, : Not applicable
FPGA register address
Register name
1000_A000H
usr_wrdat_ctrl
1000_A002H
usr_logmode_sel
1000_A004H
usr_micon_syserr
1000_A010H to 1000_A02EH
usr_alwreg_00 to usr_alwreg_0f
1000_A030H to 1000_A04EH
usr_alrreg_00 to usr_alrreg_0f
1000_B000H to 1000_B2FEH
usr_wreg_000 to usr_wreg_17f
1000_B300H to 1000_B3FEH
usr_wreg_180 to usr_wreg_1ff
1000_B800H to 1000_BAFEH
usr_rreg_000 to usr_rreg_17f
1000_BB00H to 1000_BBFEH
usr_rreg_180 to usr_rreg_1ff
Description
D/A conversion enable/disable setting
D/A conversion value selection
D/A conversion timing selection
DAC LDAC signal selection
D/A conversion value CH0 (E0)
D/A conversion value CH1 (E0)
D/A conversion value CH0 (E1)
D/A conversion value CH1 (E1)
D/A conversion value CH0 (E2)
D/A conversion value CH1 (E2)
Description
Logging operation control register
Logging state register
Logging system flag
Flag clear register
Logging data size setting
Time information (year)
Time information (month, day, hour)
Time information (minute, second)
Time information (ms)
Time information (s)
Set number of sampling after trigger (lower side)
Set number of sampling after trigger (upper side)
Number of samplings (lower)
Number of samplings (upper)
Description
Write/read data control register
User circuit logging mode selection
MCU system error notification
Always write register
Always read register
Write data (transient area)
Write data (cyclic area)
Read data (transient area)
Read data (cyclic area)
Type
Read
Write
Parameter
Parameter
Parameter
Parameter
Control
Control
Control
Control
Control
Control
Type
Read
Write
Monitor
Monitor
Parameter
Monitor
Monitor
Monitor
Monitor
Monitor
Parameter
Parameter
Monitor
Monitor
Type
Read
Write
Parameter
Control
Monitor
Control/
parameter
Control
Monitor
Monitor
APPX
Appendix 4 FPGA register
A
509
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Troubleshooting
