Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 523

External reset ON/OFF setting
■Address
Name
If the external reset ON/OFF setting (ioport_set)
■Description
Sets ON (issued) or OFF (not issued) for the reset issued to the circuit board when FPGA control is stopped (when the
internal operation start/stop is stop).
The external output when ON differs depending on the circuit board type.
• DC I/O circuit board: OFF
• Differential I/O circuit board: Hi-Z
• Analog I/O circuit board: 0V/0mA
The external output when OFF differs depending on the circuit board type.
• DC I/O circuit board: Previous value held
• Differential I/O circuit board: "CLEAR (L fixed output)", "CLEAR (H fixed output)", and " HOLD (previous value hold)" can be
set by "Differential output HOLD/CLEAR" setting.
• Analog I/O circuit board: Previous value held external reset ON/OFF setting (E0 to E2)
b15 b14 b13 b12
0 (fixed)
(1) External reset ON/OFF setting (B0)
• 1: Reset OFF
• 0: Reset ON
(2) External reset ON/OFF setting (B1)
• 1: Reset OFF
• 0: Reset ON
(3) External reset ON/OFF setting (B2)
• 1: Reset OFF
• 0: Reset ON
(4) External reset ON/OFF setting (E0 to E2)
• 1: Reset OFF
• 0: Reset ON
■FPGA initial value
0
■Firmware initial value
0
■Reset cause
Reset
■Precautions and restrictions
• Changes to this register when b0 of internal operation start/stop (mode_ctrl2) (FPGA register address: 1000_0002H) is
stopped (0) are immediately reflected.
• Settings cannot be made by the FPGA register access function. Set from the FPGA Module Configuration Tool.
b11 b10 b9 b8 b7 b6 b5 b4
FPGA register address
1000_0020H
b3 b2 b1 b0
(4) (3) (2) (1)
APPX
521
Appendix 4 FPGA register
A