Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 698

No. Target Corresponding part
file
6 *.map.rpt Warning (10230): Verilog HDL assignment warning at
altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of
target (1) File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1170
Warning (10230): Verilog HDL assignment warning at
altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of
target (1) File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1171
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write"
assigned a value but never read File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
altera_merlin_width_adapter.sv Line: 283
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(742): object "aligned_addr"
assigned a value but never read File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
altera_merlin_width_adapter.sv Line: 742
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(743): object
"aligned_byte_cnt" assigned a value but never read File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
altera_merlin_width_adapter.sv Line: 743
Warning (113015): Width of data items in "nios_fw_mem.hex" is greater than the memory width. Wrapping data
items to subsequent addresses. Found 960 warnings, reporting 10 File: C:/FPGA_release/RTL/TOP/PT/
mem_init/nios_fw_mem.hex Line: 1
Warning (113009): Data at line (2) of memory initialization file "nios_fw_mem.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_fw_mem.hex Line: 2
Warning (113009): Data at line (3) of memory initialization file "nios_fw_mem.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_fw_mem.hex Line: 3
Warning (113009): Data at line (4) of memory initialization file "nios_fw_mem.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_fw_mem.hex Line: 4
Warning (113009): Data at line (5) of memory initialization file "nios_fw_mem.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_fw_mem.hex Line: 5
Warning (113009): Data at line (6) of memory initialization file "nios_fw_mem.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_fw_mem.hex Line: 6
Warning (113009): Data at line (7) of memory initialization file "nios_fw_mem.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_fw_mem.hex Line: 7
Warning (113009): Data at line (8) of memory initialization file "nios_fw_mem.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_fw_mem.hex Line: 8
Warning (113009): Data at line (9) of memory initialization file "nios_fw_mem.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_fw_mem.hex Line: 9
Warning (113009): Data at line (10) of memory initialization file "nios_fw_mem.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_fw_mem.hex Line: 10
Warning (113009): Data at line (11) of memory initialization file "nios_fw_mem.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_fw_mem.hex Line: 11
Warning (113015): Width of data items in "nios_ram_init.hex" is greater than the memory width. Wrapping data
items to subsequent addresses. Found 640 warnings, reporting 10 File: C:/FPGA_release/RTL/TOP/PT/
mem_init/nios_ram_init.hex Line: 1
Warning (113009): Data at line (2) of memory initialization file "nios_ram_init.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_ram_init.hex Line: 2
Warning (113009): Data at line (3) of memory initialization file "nios_ram_init.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_ram_init.hex Line: 3
Warning (113009): Data at line (4) of memory initialization file "nios_ram_init.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_ram_init.hex Line: 4
Warning (113009): Data at line (5) of memory initialization file "nios_ram_init.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_ram_init.hex Line: 5
Warning (113009): Data at line (6) of memory initialization file "nios_ram_init.hex" is too wide to fit in one
memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/
nios_ram_init.hex Line: 6
APPX
696
Appendix 13 Warning List
Description
Warning for IP of the
sample circuit. There is
no problem.