Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 528

Data update timing
■Address
Name
Data update timing (B0) (tim_iob0x_conv)
Data update timing (B1) (tim_iob1x_conv)
Data update timing (B2) (tim_iob2x_conv)
Data update timing (E0) (tim_ioe0x_conv)
Data update timing (E1) (tim_ioe1x_conv)
Data update timing (E2) (tim_ioe2x_conv)
■Description
Sets the output timing (cycle) for DC/differential (RS-422/RS-485)/analog output. (Setting unit: 0.01s)
• FFFFH: 655.36s
• FFFEH: 655.35s to 0004H: 0.05s
• 0003H: 0.04s
• 0002H: 0.03s
• 0001H: 0.02s
• 0000H: 0.01s
■FPGA initial value
0000H
■Firmware initial value
• DC I/O circuit board: 0009H (0.10s)
• Differential I/O circuit board: 0000H (0.01s)
• Analog I/O circuit board: 0257H (6.00s) (E0 to E2 only)
• No circuit board: 0009H (0.10s) (E0 to E2 only)
■Reset cause
Reset
■Precautions and restrictions
• When a DC I/O circuit board is connected to B or E, the value cannot be set to less than 0009H (0.10s).
• When an Analog I/O circuit board is connected to E, the value cannot be set to less than 0256H (6.00s). D/A conversion
timing selection (E) (aoport_da_cyc_sel) is the user circuit output (1), the setting is disabled.
APPX
526
Appendix 4 FPGA register
FPGA register address
1000_2110H
1000_2112H
1000_2114H
1000_2118H
1000_211AH
1000_211CH