Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 529

Logging cycle timing
■Address
Name
Logging cycle timing (tim_log_cyc)
■Description
Sets the logging cycle timing.
• FFFFH: 32.768ms
• FFFEH: 32.7675ms to 0003H: 2s
• 0002H: 1.5s
• 0000H to 0001H: 1s
■FPGA initial value
0000H
■Firmware initial value
0001H
■Reset cause
Reset
■Precautions and restrictions
• Settings cannot be made by the FPGA register access function. Set from the FPGA Module Configuration Tool.
• The contents of this register are in increments of 0.5s, but the FPGA Module Configuration Tool sets them in increments of
1s.
• If b13 of the logging operation control register (lgdw_ctrl) (FPGA register address: 1000_9000H) is set to user circuit output
(1), the setting is disabled.
FPGA register address
1000_2200H
APPX
527
Appendix 4 FPGA register
A