Table of Contents
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No.
Signal name
18
dig_iob2_y_clk100m_reg [15:0]
19
dig_ioe0_y_clk100m_reg [15:0]
20
dig_ioe1_y_clk100m_reg [15:0]
21
dig_ioe2_y_clk100m_reg [15:0]
22
dig_iob0_dio485_o_clk100m_reg
23
dig_iob1_dio485_o_clk100m_reg
24
dig_iob2_dio485_o_clk100m_reg
25
dig_ioe0_dio485_o_clk100m_reg
26
dig_ioe1_dio485_o_clk100m_reg
27
dig_ioe2_dio485_o_clk100m_reg
11 FPGA INTERNAL CIRCUIT
248
11.4 User Circuit Block
I/O
Logic
Function
O
Digital output signal (B2 after digital control)
O
Digital output signal (E0 after digital control)
O
Digital output signal (E1 after digital control)
O
Digital output signal (E2 after digital control)
O
Digital output signal (digital input/output B0 after
digital control)
O
Digital output signal (digital input/output B1 after
digital control)
O
Digital output signal (digital input/output B2 after
digital control)
O
Digital output signal (digital input/output E0 after
digital control)
O
Digital output signal (digital input/output E1 after
digital control)
O
Digital output signal (digital input/output E2 after
digital control)
Connection
Initial
Pulse
destination
value
signal
Logging
0000h
control part,
output block
part
Logging
0000h
control part,
output block
part
Logging
0000h
control part,
output block
part
Logging
0000h
control part,
output block
part
Output block
0b
part
Output block
0b
part
Output block
0b
part
Output block
0b
part
Output block
0b
part
Output block
0b
part
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Troubleshooting
