Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 255

Reference enable generation
The reference enable generator implements a 32-bit ring counter with the upper limit of "Pulse output part pulse width upper
limit value (lower side)/(upper side) (B0)", and outputs the 0-degree enable pulse (pls_0degree_en) for pulse generation and
90-degree enable pulse (pls_90degree_en). 0-degree enable outputs a pulse (1 pulse (clk100m)) when the bit shift (1/2) value
of "Pulse output part pulse width upper limit value (lower side)/(upper side) (B0)" and the 32-bit ring counter are equal. 90-
degree enable outputs a pulse (1 pulse (clk100m)) when the value of "Pulse output part pulse width upper limit value (lower
side)/(upper side)" and the 32-bit ring counter are equal. The block diagram and timing chart of the reference enable
generator are shown below.
■Block Diagram
Pulse output part pulse width upper limit value
(lower side)/(upper side) (B0)
re_rs_usr_wreg_110_clk100m_reg[15:0]
re_rs_usr_wreg_111_clk100m_reg[15:0]
Pulse output part pulse output enable (B0)
re_rs_usr_wreg_1b8_clk100m_reg[15:0]
*1 If 0000_0000H to 0000_0003H is input, it will be clipped to 0000_0003H.
■Timing chart
clk100m
User circuit block reset
usr_rst_n
Pulse output part pulse output enable (B0)
re_rs_usr_wreg_1b8_clk100m_reg[15:0]
Pulse output part pulse width upper limit value (lower side)/(upper side) (B0)
{re_rs_usr_wreg_111_clk100m_reg[15:0],
re_rs_usr_wreg_110_clk100m_reg[15:0]}
Pulse output reference counter
pls_base_counter_clk100m_reg[31:0]
0 degree enable
pls_0degree_en
90 degree enable
pls_90degree_en
■Pulse output, reference counter
This is a 32-bit ring counter that determines the upper limit value at "Pulse output part pulse width upper limit value (lower
side) (B0)" and "Pulse output part pulse width upper limit value (upper side) (B0)".
The truth values of the pulse output reference counter are shown below.
*1
No. usr_rst_n
1 0b (enable) X
2 1b (disable) 0b (disable)
3 1b 1b (enable)
4 1b 1b
*1 Pulse output part pulse output enable (B0)
*2 Pulse output part pulse width upper limit value (lower side)/(upper side) (B0) (value after clipping)
Reference enable generation
(uc4_plsout_engen)
pls_base_counter_clk100m_reg[31:0]
Pulse output
reference
counter
*1
(I)
(I) L
(I) L
(I)
(Internal) 3d 0d 1d
0d 1d 2d
L
(Internal)
(Internal) L
*2
X
X
*2
)  pls_base_counter_clk100m_reg
(
*2
( ) > pls_base_counter_clk100m_reg
Pulse output
enable
generation
3H
2d 3d 2d 2d
0d 1d 3d 0d 1d 3d 0d
Pulse output reference counter
0000_0000h
0000_0000h
0000_0000h
pls_base_counter_clk100m_reg+1
11 FPGA INTERNAL CIRCUIT
0 degree enable
pls_0degree_en
90 degree enable
pls_90degree_en
2d 2d
1d 3d 0d 1d 3d 0d 1d
253
11.4 User Circuit Block
11