Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 272

■D/A conversion value generation
In D/A conversion value generation, D/A conversion value is generated by "Analog output part HOLD/CLEAR",
"Microcomputer system error notification", and "Analog output part D/A conversion value CH0/CH1 (E0)". The truth table for
D/A conversion value generation is shown below.
No. usr_rst_n
1 0b (enable)
2 1b (disable)
3 1b
4 1b
5 1b
■D/A conversion value enable generation
D/A conversion value enable (E0) (uc_ioe0_andat_en_clk100m_1shot_reg) detects the rising edge (an_start_up) of "Analog
output part D/A conversion value enable" and outputs it in one level of flip-flop.
■Digital input/output control
Implements an LDAC generation counter (ldac_counter_clk100m_reg[4:0]) with an upper limit value of 30d, and decodes this
counter to output a 300ns enable pulse (L enable pulse) as an LDAC signal. The LDAC generation counter and the decoding
conditions for the LDAC output signal are shown below.
• Digital input/output control counter truth table
No. usr_rst_n clk100m
1 0b (enable) X

2 1b (disable)

3 1b

4 1b
• LDAC output signal decoding condition
No. usr_rst_n clk100m
1 0b (enable) X

2 1b (disable)

3 1b

4 1b

5 1b
If "Microcomputer system error notification" occurs, output D/A conversion value enable (E0 to E2) and the
LDAC output signal (E0 to E2) at least once. Since IOB_RSTL is not output externally, the DAC value needs
to be pseudo overwritten.
11 FPGA INTERNAL CIRCUIT
270
11.4 User Circuit Block
clk100m MCU system error
notification
X X

0b (disable)

0b

1b (enable)

1b
an_start_up
X
1b (enable)
0b (disable)
0b
re_rs_usr_wreg_160_clk1
00m_reg[1:0]
X
00b or 11b
01b
10b
10b
Analog output part HOLD/
CLEAR
X
0b(CLEAR)
1b(HOLD)
0b
1b
ldac_counter_clk100m_reg[4:0]
X
X
ldac_counter_clk100m_reg < 1Eh
ldac_counter_clk100m_reg  1Eh
ldac_counter_clk100m_reg[4:0]
X
X
X
ldac_counter_clk100m_reg < 1Eh
ldac_counter_clk100m_reg  1Eh
uc_ioe0_andat_clk100m_reg
0000_0000h
{re_rs_usr_wreg_1c1_clk100m_reg,
re_rs_usr_wreg_1c0_clk100m_reg,}
{re_rs_usr_wreg_1c1_clk100m_reg,
re_rs_usr_wreg_1c0_clk100m_reg,}
0000_0000h
Previous value held
LDAC generation counter
(ldac_counter_clk100m_reg[4:0])
1Eh
00h
ldac_counter_clk100m_reg+1
1Eh
LDAC output signal
(uc_ioe0_ldac_clk100m_reg[1:0])
11b
11b
00b
00b
11b