Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 258

Counter control part (uc3_cnt_top)
This module implements a counter controlled by digital signals input from the digital input control part. The counter
implements a 32-bit ring counter (2-phase multiple of 4) and a 32-bit ring counter (1-phase multiple of 1). The block diagram,
function list, and terminal list of the counter control part block are shown below.
■Counter control part block diagram
Counter control part 32-bit ring counter
(2-phase multiple of 4) input signal selection (B0) [5]
re_rs_usr_wreg_0a5_clk100m_reg[5]
Counter control part 32-bit ring counter
(2-phase multiple of 4) input signal selection (B0) [13]
re_rs_usr_wreg_0a5_clk100m_reg[13]
Counter control part 32-bit ring counter
(2-phase multiple of 4) input signal selection (B0) [4:0]
re_rs_usr_wreg_0a5_clk100m_reg[4:0]
Counter control part 32-bit ring counter
(2-phase multiple of 4) input signal selection (B0) [12:8]
re_rs_usr_wreg_0a5_clk100m_reg[12:8]
Digital input signal (B0 after filtering)/
digital input signal (digital I/O B0 after filtering)
sim_iob0_x_clk100m_reg[15:0],
sim_iob0_dio485_i_clk100m_reg
Register setting value
re_rs_usr_wreg_188_clk100m_reg[0]
re_rs_usr_wreg_0189_clk100m_reg[15:0],
re_rs_usr_wreg_18a_clk100m_reg[15:0]
re_rs_usr_wreg_0a3_clk100m_reg[15:0],
re_rs_usr_wreg_0a4_clk100m_reg[15:0]
Counter control part 32-bit ring counter
(1-phase multiple of 1) input signal selection (B0) [5]
re_rs_usr_wreg_0d5_clk100m_reg[5]
Counter control part 32-bit ring counter
(1-phase multiple of 1) input signal selection (B0) [13]
re_rs_usr_wreg_0d5_clk100m_reg[13]
Counter control part 32-bit ring counter
(1-phase multiple of 1) input signal selection (B0) [4:0]
re_rs_usr_wreg_0d5_clk100m_reg[4:0]
Counter control part 32-bit ring counter
(1-phase multiple of 1) input signal selection (B0) [12:8]
re_rs_usr_wreg_0d5_clk100m_reg[12:8]
Digital input signal (B0 after filtering)/
digital input signal (digital I/O B0 after filtering)
sim_iob0_x_clk100m_reg[15:0],
sim_iob0_dio485_i_clk100m_reg
Register setting value
re_rs_usr_wreg_1a0_clk100m_reg[0]
re_rs_usr_wreg_1a1_clk100m_reg[15:0],re_rs_usr_
wreg_1a2_clk100m_reg[15:0]
re_rs_usr_wreg_0d3_clk100m_reg[15:0],re_rs_usr_
wreg_0d4_clk100m_reg[15:0]
*1 B1, B2, E0, E1, and E2 also have the same structure.
11 FPGA INTERNAL CIRCUIT
256
11.4 User Circuit Block
Counter control part (uc3_cnt_top)
32-bit ring counter (2-phase multiple of 4)
(uc4_cnt_32ring_2pha4multi)
Counter control (2-phase multiple of 4)
(uc5_cnt_counter_ctl_2pha4multi)
Phase A
Phase B
0000_0000H
32-bit ring counter (1-phase multiple of 1)
(uc4_cnt_32ring_1pha1multi)
Counter control (1-phase multiple of 1)
(uc5_cnt_counter_ctl_1pha1multi)
Phase A
Phase Z
0000_0000H
*1
Counter (32 bits)
(uc5_cnt_counter32)
UP UP COUNT
DOWN DOWN
PRE
PREDATA
UP_LIM
DOWN_LIM
1b RING/LIN
*1
Counter (32 bits)
(uc5_cnt_counter32)
UP UP COUNT
DOWN DOWN
PRE
PREDATA
UP_LIM
DOWN_LIM
1b RING/LIN
32-bit ring counter (2-phase
multiple of 4) phase A input (B0)
cnt_iob0_32ring_2pha4multi_pha
32-bit ring counter (2-phase
multiple of 4) phase B input (B0)
cnt_iob0_32ring_2pha4multi_phb
32-bit ring counter (2-phase
multiple of 4) counter value (B0)
cnt_iob0_32ring_2pha4multi_counter_
clk100m_reg[31:0]
32-bit ring counter (1-phase
multiple of 1) phase A input (B0)
cnt_iob0_32ring_1pha1multi_pha
32-bit ring counter (1-phase
multiple of 1) Phase Z input (B0)
cnt_iob0_32ring_1pha1multi_phz
32-bit ring counter (1-phase
multiple of 1) counter value (B0)
cnt_iob0_32ring_1pha1multi_counter_
clk100m_reg[31:0]