Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 640

Connection destination
Block name Instance
name
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
APPX
638
Appendix 5 List of User Circuit Block Terminals
Terminal
signal Signal name
re_rs_usr_rreg_0a Read data 163
3_clk100m_reg
re_rs_usr_rreg_0a Read data 164
4_clk100m_reg
re_rs_usr_rreg_0a Read data 165
5_clk100m_reg
re_rs_usr_rreg_0a Read data 166
6_clk100m_reg
re_rs_usr_rreg_0a Read data 167
7_clk100m_reg
re_rs_usr_rreg_0a Read data 168
8_clk100m_reg
re_rs_usr_rreg_0a Read data 169
9_clk100m_reg
re_rs_usr_rreg_0a Read data 170
a_clk100m_reg
re_rs_usr_rreg_0a Read data 171
b_clk100m_reg
re_rs_usr_rreg_0a Read data 172
c_clk100m_reg
re_rs_usr_rreg_0a Read data 173
d_clk100m_reg
re_rs_usr_rreg_0a Read data 174
e_clk100m_reg
re_rs_usr_rreg_0af Read data 175
_clk100m_reg
re_rs_usr_rreg_0b Read data 176
0_clk100m_reg
re_rs_usr_rreg_0b Read data 177
1_clk100m_reg
re_rs_usr_rreg_0b Read data 178
2_clk100m_reg
re_rs_usr_rreg_0b Read data 179
3_clk100m_reg
re_rs_usr_rreg_0b Read data 180
4_clk100m_reg
re_rs_usr_rreg_0b Read data 181
5_clk100m_reg
re_rs_usr_rreg_0b Read data 182
6_clk100m_reg
re_rs_usr_rreg_0b Read data 183
7_clk100m_reg
re_rs_usr_rreg_0b Read data 184
8_clk100m_reg
re_rs_usr_rreg_0b Read data 185
9_clk100m_reg
re_rs_usr_rreg_0b Read data 186
a_clk100m_reg
re_rs_usr_rreg_0b Read data 187
b_clk100m_reg
re_rs_usr_rreg_0b Read data 188
c_clk100m_reg
re_rs_usr_rreg_0b Read data 189
d_clk100m_reg
re_rs_usr_rreg_0b Read data 190
e_clk100m_reg
re_rs_usr_rreg_0bf Read data 191
_clk100m_reg
Bit Input/ Polarity
width output

16 Output

16 Output

16 Output
16 Output 

16 Output

16 Output
16 Output 

16 Output

16 Output

16 Output

16 Output

16 Output
16 Output 

16 Output

16 Output

16 Output
16 Output 

16 Output

16 Output
16 Output 

16 Output

16 Output

16 Output

16 Output

16 Output
16 Output 

16 Output

16 Output

16 Output
Initial 1shot Sync clock
value
Feq

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m