Appendix 5 List Of User Circuit Block Terminals - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Appendix 5
The list of external terminals of the user circuit block is shown below.
Connection destination
Block name Instance
name
Clock control u_cc2_top
part
Reset control u_rc2_top
part
Digital input u_di2_top_b0
control part
Digital input u_di2_top_b1
control part
Digital input u_di2_top_b2
control part
Digital input u_di2_top_e0
control part
Digital input u_di2_top_e1
control part
Digital input u_di2_top_e2
control part
Digital I/O u_dio2_top_b0
control part
Digital I/O u_dio2_top_b1
control part
Digital I/O u_dio2_top_b2
control part
Digital I/O u_dio2_top_e0
control part
Digital I/O u_dio2_top_e1
control part
Digital I/O u_dio2_top_e2
control part
Analog input u_ai2_top_e0
control part
Analog input u_ai2_top_e0
control part
Analog input u_ai2_top_e0
control part
Analog input u_ai2_top_e0
control part
Analog input u_ai2_top_e0
control part
Analog input u_ai2_top_e0
control part
Analog input u_ai2_top_e0
control part
Analog input u_ai2_top_e0
control part
Analog input u_ai2_top_e0
control part
Analog input u_ai2_top_e0
control part
APPX
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Appendix 5 List of User Circuit Block Terminals

List of User Circuit Block Terminals
Terminal
signal Signal name
clk100m System clock
rst_n System reset (OR
of reset and S/W
reset)
di_iob0_x_clk100m Digital input signal
_reg (B0 after filtering)
di_iob1_x_clk100m Digital input signal
_reg (B1 after filtering)
di_iob2_x_clk100m Digital input signal
_reg (B2 after filtering)
di_ioe0_x_clk100m Digital input signal
_reg (E0 after filtering)
di_ioe1_x_clk100m Digital input signal
_reg (E1 after filtering)
di_ioe2_x_clk100m Digital input signal
_reg (E2 after filtering)
dio_iob0_dio485_i Digital input signal
_clk100m_reg (digital I/O B0 after
filtering)
dio_iob1_dio485_i Digital input signal
_clk100m_reg (digital I/O B1 after
filtering)
dio_iob2_dio485_i Digital input signal
_clk100m_reg (digital I/O B2 after
filtering)
dio_ioe0_dio485_i Digital input signal
_clk100m_reg (digital I/O E0 after
filtering)
dio_ioe1_dio485_i Digital input signal
_clk100m_reg (digital I/O E1 after
filtering)
dio_ioe2_dio485_i Digital input signal
_clk100m_reg (digital I/O E2 after
filtering)
ai_ioe0_aival_vald A/D conversion
_clk100m_reg value enable (E0)
ai_ioe0_aival_0_cl A/D conversion
k100m_reg value CH0(E0)
ai_ioe0_aival_1_cl A/D conversion
k100m_reg value CH1(E0)
ai_ioe0_aival_2_cl A/D conversion
k100m_reg value CH2(E0)
ai_ioe0_aival_3_cl A/D conversion
k100m_reg value CH3(E0)
ai_ioe0_aival_4_cl A/D conversion
k100m_reg value CH4(E0)
ai_ioe0_aival_5_cl A/D conversion
k100m_reg value CH5(E0)
ai_ioe0_aival_6_cl A/D conversion
k100m_reg value CH6(E0)
ai_ioe0_aival_7_cl A/D conversion
k100m_reg value CH7(E0)
ai_ioe0_aival_8_cl A/D conversion
k100m_reg value CH8(E0)
Bit Input/ Polarity
width output

1 Input
1 Input L

16 Input
16 Input 

16 Input

16 Input

16 Input

16 Input

1 Input

1 Input

1 Input

1 Input

1 Input

1 Input
1 Input 

16 Input

16 Input

16 Input
16 Input 

16 Input

16 Input
16 Input 

16 Input

16 Input
Initial 1shot Sync clock
value
Feq
 
0H
0H  

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0H 100MHz

0H 100MHz

0H 100MHz

0H 100MHz

0H 100MHz

0H 100MHz
0H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz
Clock


clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m