Fpga Register Details (Timing Generator) - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

FPGA register details (timing generator)

The details of the FPGA register of the timing generator are shown below.
Filter sampling pulse
■Address
Name
Filter sampling pulse (B0) (tim_iob0x_samp)
Filter sampling pulse (B1) (tim_iob1x_samp)
Filter sampling pulse (B2) (tim_iob2x_samp)
Filter sampling pulse (E0) (tim_ioe0x_samp)
Filter sampling pulse (E1) (tim_ioe1x_samp)
Filter sampling pulse (E2) (tim_ioe2x_samp)
■Description
Sets the operation cycle of the digital filter. This setting is common to all input terminals of B and E.
b15 b14 b13 b12
0 (fixed)
• FH: Data sampling timing
• EH: 100.00s
• DH: 10.00s
• CH: 2.00s
The filter time is given by the following formula. Set each register appropriately.
• Filter time = Filter sampling pulse  Input filter counter upper limit
Set the filter time to a value with a margin from the minimum value of the ON/OFF width to be taken in as an input, taking into
consideration the delay time outside the FPGA.
The following is a rough indication for the filter time for this module.
Application
For general-purpose input
For pulse counting For DC input
For differential (RS-422/RS-485) input
■FPGA initial value
0H
■Firmware initial value
• DC I/O circuit board: FH
• Differential I/O circuit board: 0H
■Reset cause
Reset
■Precautions and restrictions
• When a DC I/O circuit board is connected to B or E, only data sampling timing (FH) can be used.
• When differential I/O circuit board is connected to B and E, data sampling timing (FH) cannot be set.
• When an analog I/O circuit board is connected to E, the setting is disabled.
b11 b10 b9 b8
• BH: 1.00s
• AH: 0.50s
• 9H: 0.40s
• 8H: 0.32s
Rough indication
60% of the minimum ON/OFF width taken as input
• 1-phase input: 10% of pulse cycle
• 2-phase input: 5% of pulse cycle
• 1-phase input: 15% of pulse cycle
• 2-phase input: 12.5% of pulse cycle
b7 b6 b5 b4
• 7H: 0.20s
• 6H: 0.16s
• 5H: 0.14s
• 4H: 0.10s
FPGA register address
1000_2000H
1000_2002H
1000_2004H
1000_2008H
1000_200AH
1000_200CH
b3 b2 b1 b0
Filter sampling pulse setting
• 3H: 0.08s
• 2H: 0.04s
• 1H: 0.02s
• 0H: 0.01s
APPX
523
Appendix 4 FPGA register
A