Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 595

Logging control part 1 enable clear
■Address
Name
Logging control part 1 enable clear (usr_wreg_181)
■Description
1 Clears the logging enable signal in enable mode.
b15 b14 b13 b12
0 (fixed)
(1) 1 logging enable clear setting
• 1: 1 enable mode clear
■FPGA initial value
0
■Firmware initial value

■Reset cause
Reset
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction
■Address
Name
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction (B0) (usr_wreg_188)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction (B1) (usr_wreg_18B)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction (B2) (usr_wreg_18E)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction (E0) (usr_wreg_191)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction (E1) (usr_wreg_194)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction (E2) (usr_wreg_197)
■Description
Enables or disables the preset of the 32-bit ring counter (2-phase multiple of 4).
b15 b14 b13 b12
0 (fixed)
(1) Presets the 32-bit ring counter (2-phase multiple of 4).
• 1: Preset enable
• 0: Preset disable
■FPGA initial value
0000H
■Firmware initial value

■Reset cause
Reset
b11 b10 b9 b8
b11 b10 b9 b8
b7 b6 b5 b4
b7 b6 b5 b4
FPGA register address
1000_B302H
b3 b2 b1 b0
(1)
FPGA register address
1000_B310H
1000_B316H
1000_B31CH
1000_B322H
1000_B328H
1000_B32EH
b3 b2 b1 b0
(1)
APPX
593
Appendix 4 FPGA register
A