Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 697

No. Target Corresponding part
file
4 *.fit.rpt Warning (332174): Ignored filter at pt2_top_ni2_top_cpu.sdc(48):
*pt2_top_ni2_top_cpu:*|pt2_top_ni2_top_cpu_nios2_oci:the_pt2_top_ni2_top_cpu_nios2_oci|pt2_top_ni2_top_
cpu_nios2_oci_debug:the_pt2_top_ni2_top_cpu_nios2_oci_debug|monitor_ready could not be matched with a
keeper File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_ni2_top_cpu.sdc Line: 48
Warning (332049): Ignored set_false_path at pt2_top_ni2_top_cpu.sdc(48): Argument <from> is an empty
collection File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_ni2_top_cpu.sdc Line: 48
Warning (332174): Ignored filter at pt2_top_ni2_top_cpu.sdc(49):
*pt2_top_ni2_top_cpu:*|pt2_top_ni2_top_cpu_nios2_oci:the_pt2_top_ni2_top_cpu_nios2_oci|pt2_top_ni2_top_
cpu_nios2_oci_debug:the_pt2_top_ni2_top_cpu_nios2_oci_debug|monitor_error could not be matched with a
keeper File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_ni2_top_cpu.sdc Line: 49
Warning (332049): Ignored set_false_path at pt2_top_ni2_top_cpu.sdc(49): Argument <from> is an empty
collection File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_ni2_top_cpu.sdc Line: 49
5 *.fit.rpt Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter
Compilation Report for more information.
6 *.map.rpt Warning (12251): Pt2_top.dc3_top: 'Quick' simulation modes are NOT timing accurate. Some simulation
memory models may issue warnings or errors
Warning (12251): Pt2_top.dc3_top.pll_bridge: pll_bridge.pll_sharing cannot be both connected and exported
Warning (12251): Pt2_top.dc3_top: dc3_top.pll_sharing must be exported, or connected to a matching conduit.
Warning (10229): Verilog HDL Expression warning at pt2_top_ni2_top_cpu.v(2098): truncated literal to match
32 bits File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_ni2_top_cpu.v Line: 2098
Warning (10229): Verilog HDL Expression warning at pt2_top_ni2_top_cpu.v(2100): truncated literal to match
32 bits File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_ni2_top_cpu.v Line: 2100
Warning (10229): Verilog HDL Expression warning at pt2_top_ni2_top_cpu.v(3859): truncated literal to match
32 bits File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_ni2_top_cpu.v Line: 3859
Warning (10229): Verilog HDL Expression warning at pt2_top_ni2_top_cpu.v(4525): truncated literal to match
32 bits File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_ni2_top_cpu.v Line: 4525
Warning (10229): Verilog HDL Expression warning at pt2_top_ni2_top_cpu.v(4527): truncated literal to match
32 bits File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_ni2_top_cpu.v Line: 4527
Warning (10036): Verilog HDL or VHDL warning at pt2_top_dc3_top_p0_acv_hard_memphy.v(461): object
"seq_calib_init_reg" assigned a value but never read File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
pt2_top_dc3_top_p0_acv_hard_memphy.v Line: 461
Warning (10230): Verilog HDL assignment warning at pt2_top_dc3_top_p0_acv_hard_memphy.v(582):
truncated value with size 4 to match size of target (1) File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
pt2_top_dc3_top_p0_acv_hard_memphy.v Line: 582
Warning (10034): Output port "ddio_phy_dqdin[179..68]" at pt2_top_dc3_top_p0_acv_hard_io_pads.v(192) has
no driver File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_dc3_top_p0_acv_hard_io_pads.v
Line: 192
Warning (10034): Output port "ddio_phy_dqdin[35..32]" at pt2_top_dc3_top_p0_acv_hard_io_pads.v(192) has
no driver File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_dc3_top_p0_acv_hard_io_pads.v
Line: 192
Warning (10036): Verilog HDL or VHDL warning at pt2_top_dc3_top_dmaster_timing_adt.sv(82): object
"in_ready" assigned a value but never read File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
pt2_top_dc3_top_dmaster_timing_adt.sv Line: 82
Warning (10036): Verilog HDL or VHDL warning at pt2_top_dc3_top_dmaster_b2p_adapter.sv(78): object
"out_channel" assigned a value but never read File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
pt2_top_dc3_top_dmaster_b2p_adapter.sv Line: 78
Warning (10230): Verilog HDL assignment warning at pt2_top_dc3_top_dmaster_b2p_adapter.sv(90): truncated
value with size 8 to match size of target (1) File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
pt2_top_dc3_top_dmaster_b2p_adapter.sv Line: 90
Warning (10230): Verilog HDL assignment warning at
altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of
target (64) File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1166
Warning (10230): Verilog HDL assignment warning at
altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of
target (1) File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1167
Warning (10230): Verilog HDL assignment warning at
altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168): truncated value with size 320 to match size of
target (1) File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1168
Warning (10230): Verilog HDL assignment warning at
altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169): truncated value with size 320 to match size of
target (1) File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/
altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1169
Description
Warning for IP of the
sample circuit. There is
no problem.
Warning for IP of the
sample circuit. There is
*1
no problem.
Warning for IP of the
sample circuit. There is
no problem.
APPX
695
Appendix 13 Warning List
A