Fpga Verification Procedure - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

10.3

FPGA Verification Procedure

Verification environment
The verification environment for the sample circuit and the configuration of the verification environment are shown below.
: Need to be changed according to the user circuit block, : Need to be changed according to the development
environment, : Do not change
TB_TOP.sv
Expected
value
comparison
Micro-
computer
R/W
25MHz
Reset
generation
Interrupt
check just
before
simulation
completion
Pattern
(FNX-
_TOP_XXXX
XXXX)
DDR3L
SDRAM
model
10 FPGA DEVELOPMENT
146
10.3 FPGA Verification Procedure
JADE_IF
(MIF)
DUT(top1)
DDR3 control
part (for high
speed
DDR3 IF
simulation)
Model/task
and others
Connector
BOARD_IF
B0
(BSLT0BUS)
Connector
BOARD_IF
B1 (BSLT1BUS)
Connector
BOARD_IF
B2
(BSLT2BUS)
BOARD_IF
(ESLT0BUS)
Connector
BOARD_IF
E0...2
(ESLT1BUS)
BOARD_IF
(ESLT2BUS)
Model
(vendor)
Data input
expected
value
DC I/O circuit board
comparison
Data input
expected
value
Differential I/O circuit board
comparison
DC I/O circuit board
Differential I/O circuit board
DC I/O circuit board
Differential I/O circuit board
DC I/O circuit board
DC I/O circuit board
DC I/O circuit board
Differential I/O circuit board
Differential I/O circuit board
Differential I/O circuit board
Data input
expected
Analog I/O circuit board
value
Analog I/O circuit board
comparison
Analog I/O circuit board