Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 287

Logging end trigger selector
The logging end trigger selector outputs the logging end trigger to be output to the logging part. It selects "Digital input signal
(B0 after filtering)" and "Digital output signal (B0 after digital control)" from "Logging control part end trigger signal selection",
and selects "Logging end trigger" from "Logging control part user logging control". It detects the rising edge of the selected
signal and outputs 1 pulse (clk100m).
A block diagram of the logging end trigger selector is shown below.
Digital input signal (B0 after filtering)
sim_iob0_x_clk100m_reg[9:0]
Digital output signal (B0 after digital control)
dig_iob0_y_clk100m_reg[9:0]
Logging control part user logging control
re_rs_usr_wreg_180_clk100m_reg[1]
Logging control part end trigger signal selection
re_rs_usr_wreg_092_clk100m_reg[7:0]
Time division logging ON
timd_divi_on_clk100m_reg
User circuit logging mode selection
re_rs_usr_logmode_sel_1_0_clk100m_reg[0]
■Logging end trigger selection
According to the value set in "Logging control part end trigger signal selection (re_rs_usr_wreg_092_clk100m_reg[7: 0])", it
selects the signal (logend_sel) to be output to the level immediately below. The signals to select are shown below. Also, the
selected signal is detected on its rising edge and output to the level immediately below.
Logging control part end trigger signal
selection
(re_rs_usr_wreg_092_clk100m_reg[7:0])
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
Except for that shown above
The combination of "Time division logging ON (timd_divi_on_clk100m_reg)" generates "Time division logging end trigger
signal (timd_divi_gen_logend_clk100m_reg)". The truth table of the time division logging end trigger signal is shown below.
Time division logging ON
(timd_divi_on_clk100m_reg)
1b (enable)
0b (disable)
0b
Logging control part (uc3_log_top)
Logging end trigger selector (uc4_log_endsel)
logend_sel
Logging end
timd_divi_gen_logend_
trigger clk100m_reg
selection
logen_sel
sim_iob0_x_clk100m_reg[0]
sim_iob0_x_clk100m_reg[1]
sim_iob0_x_clk100m_reg[2]
sim_iob0_x_clk100m_reg[3]
sim_iob0_x_clk100m_reg[4]
sim_iob0_x_clk100m_reg[5]
sim_iob0_x_clk100m_reg[6]
sim_iob0_x_clk100m_reg[7]
sim_iob0_x_clk100m_reg[8]
sim_iob0_x_clk100m_reg[9]
dig_iob0_y_clk100m_reg[0]
dig_iob0_y_clk100m_reg[1]
dig_iob0_y_clk100m_reg[2]
dig_iob0_y_clk100m_reg[3]
dig_iob0_y_clk100m_reg[4]
dig_iob0_y_clk100m_reg[5]
dig_iob0_y_clk100m_reg[6]
dig_iob0_y_clk100m_reg[7]
dig_iob0_y_clk100m_reg[8]
dig_iob0_y_clk100m_reg[9]
re_rs_usr_wreg_180_clk100m_reg[1]
0b
Logging end trigger selection signal
(uc_logend_sel)

1b
0b
Rising
uc_logend_up_sel
logend_up
edge
0b
detection
1b
timd_divi_gen_
logend_up
S Q
Rising
edge
R
detection
S>R
Description
Digital input signal of IOB0_X[0] (B0 after filtering)
Digital input signal of IOB0_X[1] (B0 after filtering)
Digital input signal of IOB0_X[2] (B0 after filtering)
Digital input signal of IOB0_X[3] (B0 after filtering)
Digital input signal of IOB0_X[4] (B0 after filtering)
Digital input signal of IOB0_X[5] (B0 after filtering)
Digital input signal of IOB0_X[6] (B0 after filtering)
Digital input signal of IOB0_X[7] (B0 after filtering)
Digital input signal of IOB0_X[8] (B0 after filtering)
Digital input signal of IOB0_X[9] (B0 after filtering)
Digital output signal of IOB0_Y[0] (B0 after digital control)
Digital output signal of IOB0_Y[1] (B0 after digital control)
Digital output signal of IOB0_Y[2] (B0 after digital control)
Digital output signal of IOB0_Y[3] (B0 after digital control)
Digital output signal of IOB0_Y[4] (B0 after digital control)
Digital output signal of IOB0_Y[5] (B0 after digital control)
Digital output signal of IOB0_Y[6] (B0 after digital control)
Digital output signal of IOB0_Y[7] (B0 after digital control)
Digital output signal of IOB0_Y[8] (B0 after digital control)
Digital output signal of IOB0_Y[9] (B0 after digital control)
Logging control part: User logging control [1]
Fixed to 0.
Time division logging end trigger signal
(timd_divi_gen_logend_clk100m_reg)
Hold the previous value.
1b
0b
Logging end trigger
D Q
uc_logend_clk100m_reg
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
11
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