Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 112

■NZ2EX2S-D41A01
Item
Reset control External reset ON/OFF
part setting
Timing control Data sampling timing
part setting
Filter sampling pulse
Data update timing
Logging cycle timing
Digital input Input filter upper limit
control part value X0 to Input filter
setting upper limit value XF
Digital output Output signal selection
control part Y0 to Output signal
setting selection YF
Differential output HOLD/
CLEAR Y0 to Differential
output HOLD/CLEAR Y7
Digital I/O Select output signal or I/O
control part direction signal
setting
I/O direction setting
Input filter upper limit
value
Differential output HOLD/
CLEAR
Analog input A/D conversion enable/
control part disable setting
setting
ADC range setting CH0 to
ADC range setting CHB
ADC offset value CH0 to
ADC offset value CHB
Select A/D conversion
timing
ADC oversampling ratio
setting
Analog output D/A conversion enable/
control part disable setting CH0, D/A
setting conversion enable/
disable setting CH1
DAC range setting CH0,
DAC range setting CH1
DAC offset value CH0,
DAC offset value CH1
Select D/A conversion
value
Select D/A conversion
timing
Select DAC LDAC
signal
8 FPGA MODULE CONFIGURATION TOOL
110
8.6 Parameter Setting Function
Description
Sets ON/OFF of the reset issued to the
board when FPGA control is stopped.
*5
Sets the sampling timing (cycle) for DC
input, differential (RS-422/RS-485) input,
and analog input.
It is masked and cannot be set.
*6
Sets the output timing (cycle) for DC
output, differential (RS-422/RS-485)
output, and analog output.
*1
Sets the logging cycle.
It is masked and cannot be set.
It is masked and cannot be set.
It is masked and cannot be set.
It is masked and cannot be set.
It is masked and cannot be set.
It is masked and cannot be set.
It is masked and cannot be set.
Enables or disables A/D conversion.
Sets the ADC range.
*2
Sets the ADC offset value.
*2
Select the ADC A/D conversion timing.
*2
Sets the ADC oversampling ratio.
*2
Enables or disables D/A conversion.
Sets the DAC range.
*3
Sets the DAC offset value.
*3
Select the D/A conversion value to output
*3
to DAC.
Select the DAC D/A conversion timing.
*3
Select the LDAC signal to output to the
*3
DAC.
Setting range
• ON
• OFF
4.00s to 655.36s (set in units of
0.01s)
6.00s to 655.36s (set in units of
0.01s)
1s to 32768s (set in units of 1s)
• Conversion-disable
• Conversion-enable
• -19.8mA to 19.8mA
• -9.9V to 9.9V
-128 to 127
• Data sampling timing
• User circuit output
• No setting
• Double
• 4x
• 8x
• 16x
• 32x
• 64x
• 128x
• 256x
• Conversion-disable
• Conversion-enable
• -9.9V to 9.9V
• 0.2mA to 19.8mA
-32768 to 32767
• Register setting value
• User circuit output
• Data update timing
• User circuit output
• Fixed to Low
• User circuit output
Default
ON
4.00s
Data sampling timing
6.00s
1s
4000
Register setting
value (RY)
CLEAR (fixed to H)
Register setting
value (RY or I/O
direction)
Input
4000
CLEAR (fixed to H)
Conversion-disable
-9.9V to 9.9V
0
Data sampling timing
No setting
Conversion-disable
-9.9V to 9.9V
0
Register setting
value
Data update timing
Fixed to Low