Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 623

Connection destination
Block name Instance
name
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Terminal
signal Signal name
re_rs_usr_wreg_0 Write data 238
ee_clk100m_reg
re_rs_usr_wreg_0 Write data 239
ef_clk100m_reg
re_rs_usr_wreg_0f Write data 240
0_clk100m_reg
re_rs_usr_wreg_0f Write data 241
1_clk100m_reg
re_rs_usr_wreg_0f Write data 242
2_clk100m_reg
re_rs_usr_wreg_0f Write data 243
3_clk100m_reg
re_rs_usr_wreg_0f Write data 244
4_clk100m_reg
re_rs_usr_wreg_0f Write data 245
5_clk100m_reg
re_rs_usr_wreg_0f Write data 246
6_clk100m_reg
re_rs_usr_wreg_0f Write data 247
7_clk100m_reg
re_rs_usr_wreg_0f Write data 248
8_clk100m_reg
re_rs_usr_wreg_0f Write data 249
9_clk100m_reg
re_rs_usr_wreg_0f Write data 250
a_clk100m_reg
re_rs_usr_wreg_0f Write data 251
b_clk100m_reg
re_rs_usr_wreg_0f Write data 252
c_clk100m_reg
re_rs_usr_wreg_0f Write data 253
d_clk100m_reg
re_rs_usr_wreg_0f Write data 254
e_clk100m_reg
re_rs_usr_wreg_0f Write data 255
f_clk100m_reg
re_rs_usr_wreg_1 Write data 256
00_clk100m_reg
re_rs_usr_wreg_1 Write data 257
01_clk100m_reg
re_rs_usr_wreg_1 Write data 258
02_clk100m_reg
re_rs_usr_wreg_1 Write data 259
03_clk100m_reg
re_rs_usr_wreg_1 Write data 260
04_clk100m_reg
re_rs_usr_wreg_1 Write data 261
05_clk100m_reg
re_rs_usr_wreg_1 Write data 262
06_clk100m_reg
re_rs_usr_wreg_1 Write data 263
07_clk100m_reg
re_rs_usr_wreg_1 Write data 264
08_clk100m_reg
re_rs_usr_wreg_1 Write data 265
09_clk100m_reg
re_rs_usr_wreg_1 Write data 266
0a_clk100m_reg
Bit Input/ Polarity Initial
width output value

16 Input 0000H
16 Input  0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H
16 Input  0000H
Appendix 5 List of User Circuit Block Terminals
1shot Sync clock
Feq Clock

100MHz clk100m
 100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m
 100MHz clk100m
APPX
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