Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 606

Digital input (after filtering) IOB0_DIO485_I
■Address
Name
Digital input (after filtering) IOB0_DIO485_I (B0) (usr_rreg_183)
Digital input (after filtering) IOB0_DIO485_I (B1) (usr_rreg_185)
Digital input (after filtering) IOB0_DIO485_I (B2) (usr_rreg_187)
Digital input (after filtering) IOB0_DIO485_I (E0) (usr_rreg_189)
Digital input (after filtering) IOB0_DIO485_I (E1) (usr_rreg_18B)
Digital input (after filtering) IOB0_DIO485_I (E2) (usr_rreg_18D)
■Description
Stores the digital input (after filtering) IOB0_DIO485_I.
■FPGA initial value
0000H
■Firmware initial value

■Reset cause
Reset
A/D conversion value enable status
■Address
Name
A/D conversion value enable status (usr_rreg_18E)
■Description
Stores the enable/disable of the A/D conversion value of E.
It is enabled at the timing when the A/D conversion value is input from the ADC to the analog input control part.
b15 b14 b13
0 (fixed)
(1) A/D conversion value enable status(E0)
• 1: Enable
• 0: Disable
(2) A/D conversion value enable status(E1)
• 1: Enable
• 0: Disable
(3) A/D conversion value enable status(E2)
• 1: Enable
• 0: Disable
■FPGA initial value
0
■Firmware initial value

■Reset cause
Reset
APPX
604
Appendix 4 FPGA register
b12 b11 b10 b9 b8 b7 b6 b5
FPGA register address
1000_BB06H
1000_BB0AH
1000_BB0EH
1000_BB12H
1000_BB16H
1000_BB1AH
FPGA register address
1000_BB1CH
b4 b3 b2 b1
(3) (2)
b0
(1)