Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 268

■Counter (0.5s)
Implements a 16-bit ring counter that counts up with the 0.5s sampling pulse (tg_05us_tmgpulse_clk100m_1shot_reg) for
user circuit. The upper limit of the counter is fixed at 0001H and count up is done at every 0.5s. The truth value of the counter
(0.5s) is shown below.
No. usr_rst_n
1 0b (enable)
2 1b (disable)
3 1b
4 1b
■Timing output (for 0.5s)
Generates the logging control pulse (pls_tmgpulse_log_clk100m_1shot_reg) used inside the user circuit according to the
0.5s sampling pulse (tg_05us_tmgpulse_clk100m_1shot_reg) for user circuit and the count value (count_05s) of the
counter (0.5s).
The truth table for pulse generation is shown below.
No. usr_rst_n
1 0b (enable)
2 1b (disable)
3 1b
4 1b
Analog output block (uc3_ao_top)
This module outputs the D/A conversion value to the analog output control part of the standard circuit according to the register
setting value and the register setting timing. The block diagram, function list, and terminal list of the analog output control part
are shown below.
■Analog output control part block diagram
Analog output part D/A conversion value
CH0/CH1 (E0)
re_rs_usr_wreg_1c0_clk100m_reg[15:0],
re_rs_usr_wreg_1c1_clk100m_reg[15:0]
Microcomputer system error notification
re_rd_usr_micon_syserr_clk100m_reg[0]
Analog output part HOLD/CLEAR
re_rs_usr_wreg_168_clk100m_reg[0]
Analog output part D/A conversion value
enable
re_rs_usr_wreg_1c6_clk100m_reg[0]
Analog output part LDAC output selection
re_rs_usr_wreg_160_clk100m_reg[1:0]
*1 E1 and E2 have the same structure.
11 FPGA INTERNAL CIRCUIT
266
11.4 User Circuit Block
clk100m tg_05us_tmgpulse_clk100m_1shot_reg
X X

0b (disable)

1b (enable)

1b
clk100m tg_05us_tmgpulse_clk100m_1shot_reg
X X

0b (disable)

1b (enable)

1b
Analog output part (uc3_ao_top)
Analog output control part (uc4_ao_anout)*
{uc_ioxx_andat_u[15:0],
D/A conversion value generation
uc_ioxx_andat_l[15:0]}
holdclr_on
D/A conversion value enable generation
uc_ioxx_andat_en
Digital I/O control
uc_ioxx_ldac[1:0]
1
Rising
edge
detection
an_start_up
ldac_counter_
ldac_dec[1:0]
clk100m_reg[4:0]
LDAC
LDAC
generation
decoding
counter
Counter (0.5us) Counter (0.5us)
(count_05us) (count_05us)
X 0000h
X Hold
0001H  count_05us
0000h
0001H > count_05us count_05us+1
Counter (0.5us) Pulse for logging
(count_05us) control
(pls_tmgpulse_log_
clk100m_1shot_reg)
X 0b
X 0b
0001h = count_05us 1b
Except for that shown 0b
above
D/A conversion value CH0/CH1 (E0)
D Q
uc_ioe0_andat_clk100m_reg[31:0]
E
clr
D/A conversion value enable (E0)
D Q
uc_ioe0_andat_en_clk100m_reg
11b 00b
LDAC output (E0)
00b 01b
D Q
10b uc_ioe0_ldac_clk100m_reg[1:0]
11b 11b