Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 263

Signal name
re_rs_usr_wreg_0dd_clk100m_reg[5]
re_rs_usr_wreg_0dd_clk100m_reg[13]
re_rs_usr_wreg_1a6_clk100m_reg[0]
re_rs_usr_wreg_1a7_clk100m_reg[15:0]
re_rs_usr_wreg_1a8_clk100m_reg[15:0]
re_rs_usr_wreg_0e3_clk100m_reg[15:0]
re_rs_usr_wreg_0e4_clk100m_reg[15:0]
re_rs_usr_wreg_0e5_clk100m_reg[4:0]
re_rs_usr_wreg_0e5_clk100m_reg[12:8]
re_rs_usr_wreg_0e5_clk100m_reg[5]
re_rs_usr_wreg_0e5_clk100m_reg[13]
re_rs_usr_wreg_1a9_clk100m_reg[0]
re_rs_usr_wreg_1aa_clk100m_reg[15:0]
re_rs_usr_wreg_1ab_clk100m_reg[15:0]
re_rs_usr_wreg_0eb_clk100m_reg[15:0]
re_rs_usr_wreg_0ec_clk100m_reg[15:0]
re_rs_usr_wreg_0ed_clk100m_reg[4:0]
re_rs_usr_wreg_0ed_clk100m_reg[12:8]
re_rs_usr_wreg_0ed_clk100m_reg[5]
re_rs_usr_wreg_0ed_clk100m_reg[13]
re_rs_usr_wreg_1ac_clk100m_reg[0]
re_rs_usr_wreg_1ad_clk100m_reg[15:0]
I/O Logic Function
I  Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (B1)
Phase A register input

I Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (B1)
Phase Z register input

I Counter control part 32-bit ring counter (1-
phase multiple of 1) preset instruction (B2)

I Counter control part 32-bit ring counter (1-
phase multiple of 1) preset data (lower side)
(B2)

I Counter control part 32-bit ring counter (1-
phase multiple of 1) preset data (upper side)
(B2)

I Counter control part 32-bit ring counter (1-
phase multiple of 1) counter upper limit value
(lower side) (B2)
I  Counter control part 32-bit ring counter (1-
phase multiple of 1) counter upper limit value
(upper side) (B2)

I Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (B2)
Phase A input selection

I Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (B2)
Phase Z input selection

I Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (B2)
Phase A register input
I  Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (B2)
Phase Z register input

I Counter control part 32-bit ring counter (1-
phase multiple of 1) preset instruction (E0)
I  Counter control part 32-bit ring counter (1-
phase multiple of 1) preset data (lower side)
(E0)

I Counter control part 32-bit ring counter (1-
phase multiple of 1) preset data (upper side)
(E0)
I  Counter control part 32-bit ring counter (1-
phase multiple of 1) counter upper limit value
(lower side) (E0)

I Counter control part 32-bit ring counter (1-
phase multiple of 1) counter upper limit value
(upper side) (E0)

I Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (E0)
Phase A input selection

I Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (E0)
Phase Z input selection
I  Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (E0)
Phase A register input

I Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (E0)
Phase Z register input
I  Counter control part 32-bit ring counter (1-
phase multiple of 1) preset instruction (E1)

I Counter control part 32-bit ring counter (1-
phase multiple of 1) preset data (lower side)
(E1)
Connection Initial Pulse
destination value signal
re2_top 0b 

re2_top 0b

re2_top 0b

re2_top 0000h

re2_top 0000h

re2_top 0000h
re2_top 0000h 

re2_top 00h

re2_top 00h

re2_top 0b
re2_top 0b 

re2_top 0b
re2_top 0000h 

re2_top 0000h
re2_top 0000h 

re2_top 0000h

re2_top 00h

re2_top 00h
re2_top 0b 

re2_top 0b
re2_top 0b 

re2_top 0000h
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
11
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