Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 153

4.
To check B0, set the register areas as shown in the table below.
When setting the register areas, set b0 of Internal operation start/stop (mode_ctrl2) (FPGA register address: 1000_0002H) to
Stop (0). When b0 is set to Stop (0), FPGA external reset (IOB0_RSTL, IOE_RSTL) becomes 0. When b0 is set to Start (1),
FPGA external reset (IOB0_RSTL, IOE_RSTL) becomes 1. The writing data register is reflected by writing Write/read data
control register (usr_wrdat_ctrl) (FPGA register address: 1000_A000H).
Register name
Output signal selection (B0) (oport_iob0y_osel)
Digital output control digital output selection (B0) (usr_wreg_078)
5.
Input 1 for 0.5s and then 0 for 0.5s to Input signal monitor register (B0) (iport_iob0x_monitor) (FPGA register address:
1000_3100H).
Check that 0 is output from b0 (IOB0_Y0) of Output signal monitor (B0) (iport_iob0y_monitor) (FPGA register address:
1000_4020H).
6.
Switch the register setting value as shown in the table below and perform step 5.
When the setting value is 0001H, check that the input value to IOB0_X0 is output from IOB0_Y0. When the setting value is
0003H, check that the inverted input value to IOB0_X0 is output from IOB0_Y0.
Register name
Digital control part enable/disable control register (IOB0_X0 B0)
(usr_wreg_000)
7.
Read the checked terminal X0 as X1 to XF to perform steps 5 and 6. Use the following table instead in step 6.
Check that the values are output where each value is obtained by replacing Y0 in steps 5 and 6 with Y1 to YF.
Register name
Digital control part enable/disable control register (IOB0_X1 B0)
(usr_wreg_001)
Digital control part enable/disable control register (IOB0_X2 B0)
(usr_wreg_002)
Digital control part enable/disable control register (IOB0_X3 B0)
(usr_wreg_003)
Digital control part enable/disable control register (IOB0_X4 B0)
(usr_wreg_004)
Digital control part enable/disable control register (IOB0_X5 B0)
(usr_wreg_005)
Digital control part enable/disable control register (IOB0_X6 B0)
(usr_wreg_006)
Digital control part enable/disable control register (IOB0_X7 B0)
(usr_wreg_007)
Digital control part enable/disable control register (IOB0_X8 B0)
(usr_wreg_008)
Digital control part enable/disable control register (IOB0_X9 B0)
(usr_wreg_009)
Digital control part enable/disable control register (IOB0_XA B0)
(usr_wreg_00A)
Digital control part enable/disable control register (IOB0_XB B0)
(usr_wreg_00B)
Digital control part enable/disable control register (IOB0_XC B0)
(usr_wreg_00C)
Digital control part enable/disable control register (IOB0_XD B0)
(usr_wreg_00D)
Digital control part enable/disable control register (IOB0_XE B0)
(usr_wreg_00E)
Digital control part enable/disable control register (IOB0_XF B0)
(usr_wreg_00F)
8.
Read B0 as B1, B2, and E0 to E2 and perform steps 4 to 7.
Check that the values are output where each value is obtained by replacing B0 in steps 5 to 7 with B1, B2, and E0 to E2.
Setting value Reference
FFFFH Page 530 Output signal selection
0000H Page 576 Digital output control digital output selection
Setting value Reference
0000H0001H0003H Page 573 Digital control part enable/disable control
register
Setting value Reference
0000H0001H0003H Page 573 Digital control part enable/disable control
register
10 FPGA DEVELOPMENT
10.3 FPGA Verification Procedure
10
151