Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 526

Data sampling timing (B)
■Address
Name
Data sampling timing (B0) (tim_iob0x_en)
Data sampling timing (B1) (tim_iob1x_en)
Data sampling timing (B2) (tim_iob2x_en)
■Description
Sets the timing (cycle) for sampling DC/differential (RS-422/RS-485). (Setting unit: 0.01s)
• FFFFH: 655.36s
• FFFEH: 655.35s to 0004H: 0.05s
• 0003H: 0.04s
• 0002H: 0.03s
• 0001H: 0.02s
• 0000H: 0.01s
■FPGA initial value
0000H
■Firmware initial value
• DC I/O circuit board: 000EH(0.15s)
• Differential I/O circuit board: 0000H(0.01s)
■Reset cause
Reset
■Precautions and restrictions
• When a DC I/O circuit board is connected to B, the value cannot be set to less than 0009H (0.10s).
• When a differential I/O circuit board is connected to B, set the same setting value as for the filter sampling pulse (B).
APPX
524
Appendix 4 FPGA register
FPGA register address
1000_2100H
1000_2102H
1000_2104H