Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Cc-link ie tsn fpga module

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CC-Link IE TSN FPGA Module

User's Manual

-NZ2GN2S-D41P01

-NZ2GN2S-D41D01

-NZ2GN2S-D41PD02

-NZ2EX2S-D41P01

-NZ2EX2S-D41D01

-NZ2EX2S-D41A01

-FPGA module configuration tool(SW1DNN-CCIETFLEXP-M)

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Troubleshooting

Summary of Contents for Mitsubishi Electric NZ2GN2S-D41P01

Page 1 CC-Link IE TSN FPGA Module User's Manual -NZ2GN2S-D41P01 -NZ2GN2S-D41D01 -NZ2GN2S-D41PD02 -NZ2EX2S-D41P01 -NZ2EX2S-D41D01 -NZ2EX2S-D41A01 -FPGA module configuration tool(SW1DNN-CCIETFLEXP-M)
Page 3: Safety Precautions
SAFETY PRECAUTIONS (Read these precautions before using this product.) Before using this product, please read this manual and the relevant manuals carefully and pay full attention to safety to handle the product correctly. If the equipment is used in a manner not specified by the manufacturer, the protection provided by the equipment may be impaired.
Page 4 [Design Precautions] CAUTION ● Do not install the communication cables together with the main circuit lines or power cables. Keep a distance of 100mm or more between them. Failure to do so may result in malfunction due to noise. ● Do not install the control lines together with the main circuit lines or power cables. Keep a distance of 150mm or more between them.
Page 5 [Wiring Precautions] WARNING ● Shut off the external power supply (all phases) used in the system before wiring. Failure to do so may result in electric shock or cause the module to fail or malfunction. [Wiring Precautions] CAUTION ● Individually ground the FG terminal of the programmable controller with a ground resistance of 100 ohms or less.
Page 6 [Startup and Maintenance Precautions] WARNING ● Do not touch any terminal while power is on. Doing so will cause electric shock or malfunction. ● Shut off the external power supply (all phases) used in the system before cleaning the module or retightening the terminal block screws or connector screws.
Page 7: Conditions Of Use For The Product
Notwithstanding the above restrictions, Mitsubishi Electric may in its sole discretion, authorize use of the PRODUCT in one or more of the Prohibited Applications, provided that the usage of the PRODUCT is limited only for the specific applications agreed to by Mitsubishi Electric and provided further that no special quality assurance or fail-safe, redundant or other safety features which exceed the general specifications of the PRODUCTs are required.
Page 8: Introduction
Note that the menu names and operating procedures may differ depending on an operating system in use and its version. When reading this manual, replace the names and procedures with the applicable ones as necessary. Relevant products NZ2GN2S-D41P01, NZ2GN2S-D41D01, NZ2GN2S-D41PD02, NZ2EX2S-D41A01, NZ2EX2S-D41P01, NZ2EX2S-D41D01...
Page 9: Fpga Development Software
FPGA DEVELOPMENT SOFTWARE  For FPGA development software (Intel Quartus Prime), use the product with the software version 20.1.1, which (its operation) has been verified by Mitsubishi Electric. (Page 26 FPGA development software)
Page 10: Table Of Contents
CONTENTS SAFETY PRECAUTIONS ..............1 CONDITIONS OF USE FOR THE PRODUCT .
Page 11 How to mount a module on a DIN rail ............63 Wiring .
Page 12 NZ2GN2S-D41P01, NZ2GN2S-D41PD02, NZ2EX2S-D41P01 ........225...
Page 13 Remote register method ..............321 Method using remote buffer memory.
Page 14 CHAPTER 18 CHECKING THE LEDS CHAPTER 19 UNIT TEST CHAPTER 20 TROUBLESHOOTING BY SYMPTOM CHAPTER 21 TROUBLESHOOTING DURING FPGA DEVELOPMENT CHAPTER 22 TROUBLE EXAMPLES of DC INPUT/OUTPUT 22.1 Troubles and Countermeasures for DC Input Circuits ........445 22.2 Troubles and Countermeasures for DC Output Circuits .
Page 15 Requirements for compliance with the Low Voltage Directive........689 Appendix 11 How to Check Production Information and Firmware Version.
Page 16: Relevant Manuals
I/O signals, remote register, remote buffer memory, and FPGA register of the FPGA module e-Manual refers to the Mitsubishi Electric FA electronic book manuals that can be browsed using a dedicated tool. e-Manual has the following features: • Required information can be cross-searched in multiple manuals.
Page 17 Standard circuit A circuit block that controls the external hardware (digital I/O circuits, analog circuits) of the FPGA. The standard circuit is provided by Mitsubishi Electric Corporation and the circuit change by users is not required. Transient transmission A function of communication with another station, which is used when requested by a dedicated instruction or an...
Page 18: Generic Terms And Abbreviations
GENERIC TERMS AND ABBREVIATIONS Unless otherwise specified, this manual uses the following generic terms and abbreviations. Generic term/abbreviation Description An abbreviation for an A/D converter. The analog input part of the standard circuit controls it. An abbreviation for a D/A converter. The analog output part of the standard circuit controls it. FPGA module An abbreviation for the CC-Link IE TSN FPGA module.
Page 19: Part 1 Overview
PART 1 OVERVIEW This part consists of the following chapters. 1 WHAT THIS MODULE CAN DO 2 PRODUCT LINEUP 3 SYSTEM CONFIGURATION...
Page 20: Chapter 1 What This Module Can Do
WHAT THIS MODULE CAN DO The FPGA module has the following features. No interface circuit design or verification required Since the FPGA module is equipped with the standard circuit, users can focus on designing and verifying the user circuit. In addition, the user circuit includes sample circuits which can be used as an example of the standard circuit connection, and this reduces the working hours required for FPGA development.
Page 21 Can be operated without GX Works3 Since the FPGA Module Configuration Tool can be connected to the FPGA module standalone, the FPGA module can be operated without GX Works3. When using the FPGA Module Configuration Tool, the initial settings required for operating the FPGA module are only selection of an FPGA module and input of the IP address.
Page 22 Configuration data can be written to the FPGA module The configuration data created with the FPGA development software can be written to the FPGA module by using the FPGA Module Configuration Tool. The user circuit can be updated via the network without reconnecting to the dedicated FPGA download cable.
Page 23: Chapter 2 Product Lineup
Model name Connection circuit board Reference CC-Link IE TSN FPGA module, DC input/output 96-point NZ2GN2S-D41P01 B0, B1, B2: DC input/output Page 34 NZ2GN2S-D41P01, DC input/ type circuit board output: 96 points CC-Link IE TSN FPGA module, differential input/output NZ2GN2S-D41D01 B0, B1, B2: Differential input/...
Page 24 MEMO 2 PRODUCT LINEUP 2.1 List of Products...
Page 25: Chapter 3 System Configuration
SYSTEM CONFIGURATION The FPGA module has the following two modes. An image of the system configuration to be used in each mode is shown. • Standalone mode • CC-Link IE TSN communication mode System configuration in standalone mode In standalone mode, the system can be controlled only by the FPGA module by setting parameters in advance using the FPGA Module Configuration Tool.
Page 26 CC-Link IE TSN communication mode In CC-Link IE TSN communication mode, the FPGA module operates as a CC-Link IE TSN remote station. ■Connection with the master station Engineering tool FPGA Module Configuration Tool (GXWorks3) USB/Ethernet Ethernet CC-Link IE TSN Master station (CPU) CC-Link IE TSN TSN HUB...
Page 27 ■Network configuration in CC-Link IE TSN communication mode The connection methods that can be used in CC-Link IE TSN communication mode are shown below. • Line topology • Ring topology • Star topology • Mixture of line topology and star topology •...
Page 28: Applicable Systems
Applicable Systems Supported master station When using the FPGA module in CC-Link IE TSN communication mode, use the following products for the master station. Model name Firmware version RJ71GN11-T2 No restriction RD78G64, RD78G32, RD78G16, RD78G8, RD78G4 RD78GHV, RD78GHW "05" or later Information on "Supported master station"...
Page 29: Part 2 Specifications
PART 2 SPECIFICATIONS This part consists of the following chapters. 4 PART NAMES 5 SPECIFICATIONS...
Page 30: Chapter 4 Part Names
PART NAMES This chapter describes the part names of the FPGA module. Main module (13) (12) (11) Extension module (10) Name Description A port for the connection to a network. (RJ45 connector) Connects an Ethernet cable. ( Page 68 Ethernet cables) There are no restrictions on the connection order of the cables for P1 and P2.
Page 31 Name Description PW LED Indicates the power supply status of the FPGA module. • On: Power supply ON • Off: Power supply OFF RUN LED Indicates the operating status of the FPGA module. • On: Operating normally • Flashing: Operating in unit test mode, updating the firmware, or initializing the stand-alone mode IP address •...
Page 32 *1 The LEDs indicate the ON/OFF status of differential I/O positive (+) signals. *2 The differential I/O terminal block has 8 points of X terminals and 8 points of Y terminals, and thus X8 to XF LEDs and Y8 to YF LEDs are always off.
Page 33 Module status and LED status in stand-alone mode FPGA module status LED status PW LED RUN LED ERR. LED FPGA RUN FPGA CONF. DATA LINK Normal operation Error Major error Moderate error Minor error Flashing Unit test In progress Flashing Completed successfully Completed with an...
Page 34: Chapter 5 Specifications
SPECIFICATIONS This chapter describes the specifications of the FPGA module. General Specifications Item Specifications Operating ambient 0 to 55 temperature Storage ambient -25 to 75 temperature Operating ambient 5 to 95%RH, non-condensing humidity Storage ambient humidity  Vibration Compliant with JIS Frequency Constant Half amplitude...
Page 35: Performance Specifications
Performance Specifications Common to the modules Item Specifications Station type Remote station CC-Link IE TSN Class CC-Link IE TSN Class B/A Network topology Line topology, star topology, mixture of star topology and line topology, ring topology CC-Link IE TSN Protocol version CC-Link IE TSN Class B: ver.1.0/2.0, CC-Link IE TSN Class A: ver.2.0 Cyclic RX/RY points...
Page 36: Main Module
Main module NZ2GN2S-D41P01, DC input/output: 96 points Item Specifications 24VDC input Number of points 48 points specifications Rated input voltage 24VDC (Ripple ratio: within 5%) (Allowable voltage range: 20.4 to 28.8VDC) Rated input current 4.2mA TYP. (for 24VDC) Maximum number of simultaneous input points...
Page 37 ■I/O terminal block I/O terminal block Terminal number Terminal number Terminal number ■Signal names of I/O terminal block Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal number name number name number name number name number name number name X0 to X3...
Page 38 NZ2GN2S-D41D01, differential input/output: 51 points Item Specifications Differential (RS-422) input Number of points 24 points specifications Pulse input speed (maximum speed) Multiple of 1 (1 phase/2 phases) 2.5Mpps Multiple of 2 (1 phase/2 phases) 5Mpps Multiple of 4 (2 phases) 10Mpps OFF ...
Page 39 ■Signal names of I/O terminal block Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal number name number name number name number name number name number name 5 SPECIFICATIONS 5.2 Performance Specifications...
Page 40 NZ2GN2S-D41PD02, DC input/output: 64 points/differential input/output: 17 points Item Specifications 24VDC input specifications Number of points 32 points Rated input voltage 24VDC (Ripple ratio: within 5%) (Allowable voltage range: 20.4 to 28.8VDC) Rated input current 4.2mA TYP. (for 24VDC) Maximum number of simultaneous input points 32 points (100%) ON voltage/ON current 11VDC or more/3mA or more and 5mA or less...
Page 41 *3 For a device to be connected to the I/O part, use a SELV power supply that meets LIM or UL 1310 Class 2. *4 The current consumption value (800mA) described on the rating plate and in the manual included with a product (Before Using the Product (BCN-P5999-1587)) is the maximum value for when the extension module is connected.
Page 42 ■I/O terminal block I/O terminal block Terminal number Terminal number Terminal number ■Signal names of I/O terminal block Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal number name number name number name number name number name number name X0 to X3...
Page 43: Extension Module
Extension module NZ2EX2S-D41P01, DC input/output: 96 points Item Specifications 24VDC input specifications Number of points 48 points Rated input voltage 24VDC (Ripple ratio: within 5%) (Allowable voltage range: 20.4 to 28.8VDC) Rated input current 4.2mA TYP. (for 24VDC) Maximum number of simultaneous input 48 points (100%) points ON voltage/ON current...
Page 44 ■I/O terminal block I/O terminal block Terminal number Terminal number Terminal number ■Signal names of I/O terminal block Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal number name number name number name number name number name number name X0 to X3...
Page 45 NZ2EX2S-D41D01, differential input/output: 51 points Item Specifications Differential (RS-422) input specifications Number of points 24 points Pulse input speed (maximum Multiple of 1 (1 phase/2 2.5Mpps speed) phases) Multiple of 2 (1 phase/2 5Mpps phases) Multiple of 4 (2 phases) 10Mpps OFF ...
Page 46 ■I/O terminal block I/O terminal block Terminal number Terminal number Terminal number 5 SPECIFICATIONS 5.2 Performance Specifications...
Page 47 ■Signal names of I/O terminal block Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal number name number name number name number name number name number name 5 SPECIFICATIONS 5.2 Performance Specifications...
Page 48 NZ2EX2S-D41A01, analog input/output: 42 points Item Specifications Analog input Number of points 36 points specifications Input range Voltage -9.9 to 9.9VDC (input resistance: 800k or more) Current -19.8 to 19.8mADC (input resistance: 1250.1%) Digital output 16-bit signed binary value (-32768 to 32767) I/O characteristics, resolution Input range A/D conversion...
Page 49 ■I/O terminal block I/O terminal block Terminal number Terminal number Terminal number ■Signal names of I/O terminal block Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal number name number name number name number name number name number name 5 SPECIFICATIONS...
Page 50 Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal Terminal Signal number name number name number name number name number name number name 1 VI 1 VI 5 SPECIFICATIONS 5.2 Performance Specifications...
Page 51: Ethernet Communication Specifications
Ethernet Communication Specifications This section describes the Ethernet communication specifications of the FPGA module. Item Description Transmission Data transmission speed 1Gbps or 100Mbps specifications Communication mode 1000BASE-T Full-duplex 100BASE-TX Interface RJ45 connector (AUTO MDI/MDI-X) Maximum frame size 1518 bytes Maximum segment length 100m Number of cascade 1000BASE-T...
Page 52 MEMO 5 SPECIFICATIONS 5.4 FPGA Performance...
Page 53: Part 3 Start-Up Procedures
PART 3 START-UP PROCEDURES This part consists of the following chapters. 6 PROCEDURES BEFORE OPERATION 7 INSTALLATION AND WIRING...
Page 54: Chapter 6 Procedures Before Operation
PROCEDURES BEFORE OPERATION This chapter describes the procedures before operation. When using standalone mode Creating configuration data Create FPGA configuration data. Page 140 FPGA DEVELOPMENT Setting the IP address/station number setting switches Set the fourth octet of the IP address for the FPGA module. Page 54 IP address/station number setting switch setting Setting the function setting switches Set the operation mode and communication speed.
Page 55 When using CC-Link IE TSN communication mode Creating configuration data Create FPGA configuration data. Page 140 FPGA DEVELOPMENT Setting the IP address/station number setting switches Set the fourth octet of the IP address for the FPGA module. Page 54 IP address/station number setting switch setting Setting the function setting switches Set the operation mode and communication speed.
Page 56: Chapter 7 Installation And Wiring
INSTALLATION AND WIRING This chapter describes the installation and wiring of the FPGA module. Setting Switches IP address/station number setting switch setting Set the IP address fourth octet using the IP address/station number setting switches on the front of FPGA module. The setting of IP address/station number setting switches is enabled when the FPGA module is powered on.
Page 57 Setting range The setting value must be in the range between 1 and 254. When a value outside the range between 1 to 254 is set, the following occurs. • When 0 is set, the FPGA module operates with the IP address stored in the non-volatile memory of the module. •...
Page 58 ■In CC-Link IE TSN communication mode The FPGA module operates with the following IP address and subnet mask until the module starts a data link with the master station after power-on. IP address/station number IP address Subnet mask setting switch status First octet to third octet Fourth octet 192.168.3.250...
Page 59 Initializing IP address in stand-alone mode In stand-alone mode, the FPGA module can initialize the IP address and the subnet mask stored in the non-volatile memory. The initialized IP address and subnet mask are as follows. • IP address: 192.168.3.250 •...
Page 60: Setting The Function Setting Switches
Setting the function setting switches Set the following functions using the DIP switch on the front of FPGA module. • Operation mode setting function • CC-Link IE TSN Class setting function • Communication speed setting function • Lock function of FPGA download via Ethernet •...
Page 61 Switch name Function name Setting details Function setting USER Always write register Sets the always write register 0 (usr_alwreg_00). Connect the always write register 0 switch 7 to function write function (usr_alwreg_00) in the user circuit so that the operation of the user circuit can be setting switch 10 changed by turning ON/OFF the user switch.
Page 62: Installation Environment And Installation Position
Installation Environment and Installation Position Installation environment Installation location Do not install the FPGA module to the following environment: • Ambient temperature is outside the range of 0 to 55; • Ambient humidity is outside the range of 5 to 95% RH; •...
Page 63: Installation
Installation Connecting an extension module By connecting the FPGA module to an extension module, the number of digital input points and digital output points can be increased, or analog input and analog output can be added. Only one extension module can be connected to a main module. There are no restrictions on the combinations of a main module and an extension module.
Page 64 Removal procedure Disconnect the extension module by reversing the procedure above. Precautions Shut off the external power supply (all phases) used in the system before connecting or removing the extension module. 7 INSTALLATION AND WIRING 7.3 Installation...
Page 65: How To Mount A Module On A Din Rail
How to mount a module on a DIN rail The method for fixing the DIN rail stopper is an example. Fix the module in accordance with the manual for the DIN rail stopper used. Mount procedure Pull down all DIN rail hooks on the back of the module until they click.
Page 66 Hang the upper hook of the stopper to the upper of the DIN rail. Slide the stopper (1) up to the left side of the module. Hold the stopper (1) in the direction opposite to the arrow on the stopper and tighten the screw with a screwdriver.
Page 67 Removal procedure Remove the module from the DIN rail by reversing the above procedure. Applicable DIN rail model (compliant with IEC 60715) • TH35-7.5Fe • TH35-7.5Al Space between DIN rail mounting screws When installing a DIN rail, tighten the screws at intervals of 200mm or less. DIN rail stopper Use a stopper that can be attached to the DIN rail.
Page 68: Wiring
Wiring Wiring to terminal block for module power supply and FG Tightening torque Tighten the terminal block mounting screws within the following tightening torque range. Overtightening the screws may damage the module case. Screw type Tightening torque range Terminal block mounting screw (M2.5 screw) 0.2 to 0.3N·m Wire to be used The following table describes the wire to be connected to the terminal block for module power supply and FG.
Page 69 Connecting and disconnecting the cable To connect the cable, fully insert a wire with a bar solderless terminal into a wire insertion opening. After inserting the wire, pull it lightly to check that it is securely clamped. Continuity can be checked with the test terminal. Use the following test plug to check continuity.
Page 70: Ethernet Cables
Ethernet cables Wiring method ■Installation procedure Power off the FPGA module and the external device. Push the Ethernet cable connector into the FPGA module until it clicks. Pay attention to the connector's orientation. Power on the FPGA module. Power on the external device. *1*2 Check that the P1 LINK LED/P2 LINK LED of the port into which the Ethernet cable is connected is on.
Page 71 Precautions ■Installing Ethernet cables • Place the Ethernet cables in a duct or clamp them. If not, dangling cable may swing or inadvertently be pulled, resulting in damage to the module or cables or malfunction due to poor contact. • Do not touch the core of the connector of the cable or the module, and protect it from dirt and dust. If any oil from your hand, or any dirt or dust sticks to the core, it can increase transmission loss, causing data link to fail.
Page 72: Wiring To I/O Terminal Block
Wiring to I/O terminal block Wire to be used The following table describes the wire to be connected to the I/O terminal block. When using the FPGA module as a UL listed product, use the wire listed below for wiring to the terminal block. Applicable wire Type Length...
Page 73 Installing and removing the I/O terminal block The following describes how to install and remove the I/O terminal block. ■Lock and release lever positions To make it easy to install and remove the I/O terminal block, a three-stage positioning stopper is attached so that the lever does not freely turn around.
Page 74 Signal names and wiring For the signal names of the I/O terminal block and wiring of the external device, refer to the specifications of each module. ( Page 33 Performance Specifications, Page 74 External Wiring) Incorrect wiring can cause malfunction of or damage on the FPGA module. Connecting and disconnecting a cable ■Connecting the cable Strip the cable as follows.
Page 75 Precautions • Use a bar solderless terminal for the wiring to the I/O terminal block. If a stripped wire is inserted to a wire insertion opening, the wire cannot be clamped securely. • Use a crimping tool to connect a bar solderless terminal to a wire. ( Page 70 Applicable solderless terminals) •...
Page 76: External Wiring
External Wiring DC input wiring This section describes the wiring to the DC input terminal. The polarity of the common can be either way, as the signal is input through the diode bridge. Note that the common terminal is common to each of four points. (Example: X0 to X3) Consider that the constant amount of input current of 4.2mA TYP.
Page 77 Precautions ■Current flow in the DC input circuit The input current at power-on is controlled to be a certain current value by the internal circuit, and thus the constant amount of current of 4.2mA TYP. (3 to 5mA) flows regardless of the input voltage. Consider this, and select connected devices and perform wiring.
Page 78 ■Transistor output type The following shows an example of wiring between the DC input terminal (1) and the NPN open collector output type (2). Power supply for sensor Output The following shows an example of wiring between the DC input terminal (1) and the NPN current output type (2). Constant- voltage circuit Output...
Page 79: Transistor Output Wiring
Transistor output wiring This is the sink output type that the current flows into the output terminal when the output element (FET) is turned on. There is a common terminal at intervals of four points. (Example: Y0 to Y3) FPGA module B0...2(E0...2) Board FPGA Board Connector...
Page 80 To prevent burnout or damage of the external devices and module if a load short-circuit occurs in the output circuit, install a fuse for each point of external terminal. The following lists the fuses whose operation has been verified by Mitsubishi Electric.
Page 81: Differential Input/Output Wiring
Differential input/output wiring The differential input/output has receivers and transceivers that satisfy the requirements of the TIA/EIA-422-B and TIA/EIA- 485-A standards. When an external device has a common terminal, connecting the common terminal is recommended because a potential difference between the common of external device and the common of module can cause the module to fail or malfunction. There is a common terminal for input terminals and output terminals at intervals of eight points and a common terminal for I/O shared terminals at intervals of one point.
Page 82 FPGA module B0...2(E0...2) Board FPGA Board Equivalent to AM26LV32 Shielded twisted pair cable (with a built-in fail-safe circuit) Connector FPGA IOB0...2_X0 (IOE0...2_X0) 150Ω · · · · Shielded twisted pair cable IOB0...2_X3 (IOE0...2_X3) 150Ω Equivalent to AM26LV32 Shielded twisted pair cable (with a built-in fail-safe circuit) IOB0...2_X4 (IOE0...2_X4)
Page 83: Analog Input Wiring
Analog input wiring Using a voltage input signal FPGA module E0...2 Board FPGA Board ADC0 Connector FPGA IOE0...2_X1 Signal source IOE0...2_X0 AD CH0...CH3 -9.9...9.9V IOE0...2_X2 IOE0...2_X4 800kΩ IOE0...2_X7 or more Shield IOE0...2_XOEL0 IOE0...2_XOEL1 IOE_RSTL Power supply monitoring ADC1 IOE_DCDL AD CH4...CH7 IOE0...2_X3 IOE0...2_YCK0 IOE0...2_YCK1...
Page 84 Using a current input signal FPGA module E0...2 Board FPGA Board ADC0 Connector FPGA IOE0...2_X1 Signal source AD CH0...CH3 IOE0...2_X0 -19.8...19.8mA IOE0...2_X2 · IOE0...2_X4 125Ω IOE0...2_X7 Shield IOE0...2_XOEL0 IOE0...2_XOEL1 IOE_RSTL Power supply monitoring ADC1 IOE_DCDL AD CH4...CH7 IOE0...2_X3 · IOE0...2_YCK0 IOE0...2_YCK1 ADC2 AD CH8...CHB...
Page 85 Precautions To obtain the maximum performance from the A/D conversion function and improve the system reliability, external wiring that is noise resistant is required. Precautions for external wiring are as follows. • Use separate cables for the AC control circuit and the external input signals of the analog input terminal to avoid effects of the AC side surges or induction.
Page 86: Analog Output Wiring
Analog output wiring FPGA module E0...2 Board FPGA Board DAC0 Connector FPGA Motor drive module and others DA CH0 IOE0...2_Y2 IOE0...2_Y3 IOE0...2_Y4 IOE0...2_Y6 Shield IOE_RSTL Power supply monitoring IOE_DCDL DAC1 DA CH1 IOE0...2_Y7 *1 For the cable, use the 2-core shielded twisted pair cable. *2 If there is noise or ripples in the external wiring, connect a 0.1 to 0.47F capacitor (25V or higher voltage-resistant product) to the input terminal of the external device.
Page 87: Part 4 Settings
PART 4 SETTINGS This part consists of the following chapters. 8 FPGA MODULE CONFIGURATION TOOL 9 PARAMETER SETTING...
Page 88: Chapter 8 Fpga Module Configuration Tool
FPGA MODULE CONFIGURATION TOOL This chapter describes the FPGA Module Configuration Tool used to write to the FPGA module. For the FPGA Module Configuration Tool, please consult your local Mitsubishi representative. Starting Up and Finishing When using CC-Link IE TSN communication mode The following describes the startup method when using CC-Link IE TSN communication mode.
Page 89 When using standalone mode Here is how to start when using standalone mode. Operating procedure Start FPGAUnitSettingTool from "MELSOFT" in the Windows Start menu. The FPGA Module Configuration Tool will start. Exit In the FPGA Module Configuration Tool, select [Project]  [Exit]. 8 FPGA MODULE CONFIGURATION TOOL 8.1 Starting Up and Finishing...
Page 90: Window Configuration
Window Configuration The overall window configuration is shown below. Window Reference  Title bar Menu bar Page 91 FPGA Module Configuration Tool Menu List Menu window Page 89 Menu window Work window Page 90 Work window Guidance window Page 90 Guidance window 8 FPGA MODULE CONFIGURATION TOOL 8.2 Window Configuration...
Page 91: Menu Window
Menu window The Menu window displays a navigation menu allowing execution of each function. Item Description Reference Connection destination setting Set the connection destination FPGA module. Page 113 Connection destination setting Environment setting Set the communication settings, timeout time, and other settings on the Page 127 Environment setting personal computer side.
Page 92: Work Window
Work window This window is used when performing various settings and module operations. The window to be operated will switch when an item is selected in the menu window. The window can also be switched by pressing the  button at the top right of the window.
Page 93: Fpga Module Configuration Tool Menu List
FPGA Module Configuration Tool Menu List [Project] menu Menu Reference [Project]  [New] Page 92 Creating new projects [Project]  [Open] Page 93 Opening a project  [Project]  [Close] [Project]  [Save] Page 93 Save project [Project]  [Save as] Page 93 Save project as [Project] ...
Page 94: Project Function
Operating procedure From "New", select "Connected main module" or "Connected Extension module". [Project]  [New] Item Setting range Connected main module • NZ2GN2S-D41D01 • NZ2GN2S-D41P01 • NZ2GN2S-D41PD02 Connected Extension module • None • NZ2EX2S-D41A01 • NZ2EX2S-D41D01 • NZ2EX2S-D41P01 Click the [OK] button.
Page 95: Opening A Project
Opening a project The following describes how to load a project saved on the personal computer's hard disk or other storage media. Operating procedure Open the "Open" window. [Project]  [Open] Select the project to be opened and click the [Open] button. Saving the project How to save a project file to the hard disk of your personal computer.
Page 96: Display Function
Display Function Display language switching The display language of the FPGA Module Configuration Tool can be selected from the following three. • Japanese • English • Chinese (Simplified) Operating procedure The display language is switched from "Switch Display Language". [View]  [Switch Display Language] Select the display language and click the [OK] button.
Page 97: Parameter Setting Function
Parameter Setting Function This section describes how to set the module parameters and FPGA parameters. Module parameters Set the module parameters. By selecting the setting value on the Work window and selecting the initialization menu by right-clicking, the setting value can be initialized. Operating procedure It is done from "Module Parameter".
Page 98 Item Description Setting range Default Logging data file Logging data file name Sets whether or not to add the date, time, • Without string, date, time Without string, name setting setting and character string at the time of transfer • With date date, time to the file name of logging data transferred •...
Page 99 ■CSV Format setting Item Description Setting range Default CSV Format setting CSV Format setting 0 Sets the format to use when saving • No setting No setting (bit0~bit15) to CSV Format logging data in CSV file format. • Bit, binary format setting 26 (bit416~bit431) •...
Page 100: Fpga Parameters
• By selecting the setting value on the Work window and selecting the initialization menu by right-clicking, the setting value can be initialized. Operating procedure Do it from "FPGA parameter". [Menu]  [FPGA parameter] For NZ2GN2S-D41P01 8 FPGA MODULE CONFIGURATION TOOL 8.6 Parameter Setting Function...
Page 101 ■NZ2GN2S-D41P01 Item Description Setting range Default Reset control External reset ON/OFF Sets ON/OFF of the reset issued to the board • ON part setting when FPGA control is stopped. • OFF Timing control Data sampling timing Sets the timing (cycle) for sampling the DC input.
Page 102 Item Description Setting range Default Logging part Logging operation mode setting Select the logging operation mode. • Storage operation Storage operation setting mode mode • Trigger operation mode Buffer operation setting Select linear buffer operation or ring buffer • Linear buffer operation Linear buffer operation.
Page 103 ■NZ2GN2S-D41D01 Item Description Setting range Default Reset control External reset ON/OFF Sets ON/OFF of the reset issued to the board • ON part setting when FPGA control is stopped. • OFF Timing control Data sampling timing Sets the timing (cycle) for sampling the differential 0.01s 0.01s part setting...
Page 104 Item Description Setting range Default Analog output D/A conversion enable/disable Cannot be set. control part setting CH0, D/A conversion setting enable/disable setting CH1 DAC range setting CH0, DAC range Cannot be set. setting CH1 DAC offset value CH0, DAC offset Cannot be set.
Page 105 ■NZ2GN2S-D41PD02 Item Description Setting range Default Reset control External reset ON/OFF Sets ON/OFF of the reset issued to the • ON part setting board when FPGA control is stopped. • OFF Timing control Data sampling timing Sets the sampling timing (cycle) for DC ■B0 terminal block, B1 terminal block ■B0 terminal block, B1 part setting...
Page 106 Item Description Setting range Default Digital I/O Select output signal or I/ ■B0 terminal block, B1 terminal block ■B0 terminal block, B1 terminal block Register setting value control part O direction signal It is masked and cannot be set. It is masked and cannot be set. (RY or I/O direction) setting ■B2 terminal block...
Page 107 Item Description Setting range Default Logging part Logging operation mode Select the logging operation mode. • Storage operation mode Storage operation setting setting • Trigger operation mode mode Buffer operation setting Select linear buffer operation or ring • Linear buffer operation Linear buffer operation buffer operation.
Page 108 ■NZ2EX2S-D41P01 Item Description Setting range Default Reset control External reset ON/OFF Sets ON/OFF of the reset issued to the • ON part setting board when FPGA control is stopped. • OFF Timing control Data sampling timing Sets the timing (cycle) for sampling the DC 0.10 to 655.36s (set in units of 0.01s) 0.15s part setting...
Page 109 Item Description Setting range Default Logging part Logging operation mode Select the logging operation mode. • Storage operation mode Storage operation setting setting • Trigger operation mode mode Buffer operation setting Select linear buffer operation or ring buffer • Linear buffer operation Linear buffer operation.
Page 110 ■NZ2EX2S-D41D01 Item Description Setting range Default Reset control External reset ON/OFF Sets ON/OFF of the reset issued to the • ON part setting board when FPGA control is stopped. • OFF Timing control Data sampling timing Sets the timing (cycle) for sampling 0.01 to 0.01s 0.01s part setting...
Page 111 Item Description Setting range Default Analog output D/A conversion enable/ It is masked and cannot be set. Conversion-disable control part disable setting CH0, D/A setting conversion enable/ disable setting CH1 DAC range setting CH0, It is masked and cannot be set. -9.9V to 9.9V DAC range setting CH1 DAC offset value CH0,...
Page 112 ■NZ2EX2S-D41A01 Item Description Setting range Default Reset control External reset ON/OFF Sets ON/OFF of the reset issued to the • ON part setting board when FPGA control is stopped. • OFF Timing control Data sampling timing Sets the sampling timing (cycle) for DC 4.00s to 655.36s (set in units of 4.00s part setting...
Page 113 Item Description Setting range Default Logging part Logging operation mode Select the logging operation mode. • Storage operation mode Storage operation setting setting • Trigger operation mode mode Buffer operation setting Select linear buffer operation or ring • Linear buffer operation Linear buffer buffer operation.
Page 114 ■User circuit part parameter setting Item Description Setting value User circuit part parameter size From the start address of the FPGA register writing data (transient area) in the user 0 to 384 circuit part, set the size of FPGA parameters to be saved in non-volatile memory, in (Default: 0) word units.
Page 115: Online Functions
Online Functions The online functions are described in the following. Connection destination setting Settings for a newly created Main module, changes for an Extension module, and IP address settings are made as follows. Operating procedure The contents set in "New" are displayed. [Menu] ...
Page 116 Set the IP address of the connected FPGA module. Item Setting range IP address 1.0.0.1 to 223.255.255.254 The IP address must start with a value between 1 and 223, excluding 127. Click the [Apply] button. If there is no problem with the changes, click the [Yes] button. 8 FPGA MODULE CONFIGURATION TOOL 8.7 Online Functions...
Page 117: Communication Test
Communication test Allows for checking whether communication using the set IP address is possible. Operating procedure Display the "Connection destination setting" window. [Menu]  [Connection destination setting] Click the [Communication Test] button. Click the [OK] button. The setting is not reflected if only a communication test is performed. Click the [Apply] button to have the settings be reflected.
Page 118: Parameter Writing
Parameter writing This section describes how to write Module parameters and FPGA parameters to the FPGA module. There are two types of write destinations for parameters: memory and non-volatile memory. Writing can be performed only to memory or to both memory and non-volatile memory. Parameters written to nonvolatile memory are read back into memory when the power is turned on, so control can be started without redoing settings.
Page 119: Batch Monitor Display
Batch monitor display Displays the contents of link devices, remote buffers, or FPGA register areas. By manipulating cells on the grid, values can be changed and written. Link devices (RX/RY) can only be monitored in units of 16 points, and FPGA register areas can only be monitored in units of even numbers.
Page 120 Select Data display format and Value under Display Format. Data display format Value Display content 16-bit integer [Unsigned] Decimal Displays the current value in the range of 0 to 65535. Hexadecimal Displays the current value in four hexadecimal digits. 32-bit integer [Unsigned] Decimal Displays the current value in the range of 0 to 4294967295.
Page 121 Changing current values The current values of link devices (RY/RWw), remote buffers, and FPGA register areas can be changed as follows. • The current value of Link devices (RX/RWr) cannot be changed. • In CC-Link IE TSN communication mode, the current value of link devices (RY/RWw) cannot be changed. Operating procedure Double-click a cell in grid (1) or press the Enter key.
Page 122 The bit value will be highlighted, allowing the current value to be changed. The current value can also be changed by right-clicking a grid cell and selecting the change current value menu. Automatic monitor stop • When creating a project with "New" •...
Page 123: Module Diagnostics
Module diagnostics Displays basic information, the status of LEDs, and the status of errors of the FPGA module collectively. Operating procedure Display the "Module diagnostics" window. [Menu]  [Module diagnostics] 8 FPGA MODULE CONFIGURATION TOOL 8.7 Online Functions...
Page 124 To get the latest information, click the [Refresh] button. Item Display content Main module model (name) Displays the model name of the Main module. Extension module model (name) Displays the model name of the Extension module. F/W version Shows the firmware version. FPGA version Displays the FPGA version.
Page 125 Error details window The following describes how to check the details of an error that has occurred. Operating procedure Double-click <Display error details screen>. The "Error details" window is displayed. Executing error clear The method for executing error clear is shown below. Eliminate the cause of the error.
Page 126: Configuration Data Operation
Configuration data operation Verifies or downloads the configuration data created using the FPGA development software to the configuration ROM in the FPGA module. Operating procedure Display the "Configuration data operation" window. [Menu]  [Configuration data operation] 8 FPGA MODULE CONFIGURATION TOOL 8.7 Online Functions...
Page 127 Data verification Verifies the configuration data created using the FPGA development software and the configuration ROM in the FPGA module. Operating procedure Select the configuration data folder. The configuration data files in the selected folder are displayed. Click the [Verify data] button. The verification results are displayed.
Page 128 Download execution Downloads the configuration data created using the FPGA development software to the configuration ROM in the FPGA module. Operating procedure Select the configuration data folder. The configuration data files in the selected folder are displayed. Select the file to be downloaded. Click the [Download Execution] button.
Page 129: Optional Functions
Optional Functions Environment setting The following describes how to configure settings such as communication settings and timeout time on the personal computer side. Operating procedure Set the value in the "Environment setting" window. [Menu]  [Environment setting] Item Setting range ...
Page 130: Help Function
Help Function A check of the version of the FPGA Module Configuration Tool is provided as a help function. Checking the version of the FPGA Module Configuration Tool Perform the following to check the version of the FPGA Module Configuration Tool. Operating procedure [Help] ...
Page 131: Chapter 9 Parameter Setting
Start the FPGA Module Configuration Tool. From "New", select "Connected main module" or "Connected Extension module". [Project]  [New] Item Setting range Connected main module • NZ2GN2S-D41D01 • NZ2GN2S-D41P01 • NZ2GN2S-D41PD02 Connected Extension module • None • NZ2EX2S-D41A01 • NZ2EX2S-D41D01 • NZ2EX2S-D41P01 Click the [OK] button.
Page 132 Enter the IP address of the connected FPGA module from "Connection destination setting". [Menu]  [Connection destination setting] Click the [Communication Test] button. Click the [OK] button. Click the [Apply] button. Set the parameter value in "Module Parameter". [Menu]  [Module Parameter] 9 PARAMETER SETTING 9.1 For Standalone Mode...
Page 133 Set the values of the FPGA parameters in "FPGA parameter". [Menu]  [FPGA parameter] Write the Module parameter and FPGA parameters to the FPGA module. [Online]  [Parameter write (Memory)] or [Parameter write (Memory + Non-volatile memory)] Write destination Setting values after the FPGA module is Application powered off Memory...
Page 134: For Cc-Link Ie Tsn Communication Mode
For CC-Link IE TSN Communication Mode Assure that the network parameters have been written to the CPU module of the master station. For the setting procedure for the master station, refer to the following.  User's manual for the master station used Communication cycle interval setting When using the FPGA module in CC-Link IE TSN communication mode, set the communication cycle interval as follows.
Page 135 If an FPGA module that satisfies the following conditions does not establish a data link even if the above value is set for the communication cycle interval setting, check multiples of CC-Link IE TSN Class A (low speed) in the buffer memory of the master station (buffer memory address: 1294304). •...
Page 136 CC-Link IE TSN structure Window In this manual, "Authentication Class" is described as "CC-Link IE TSN Class". Displayed items Item Description Setting range RX Setting, RY Points Set the assignment of RX/RY points. 0 to 112 (Default value: 112) Setting Start The RX/RY start number is displayed.
Page 137 Network Configuration Setting Operating procedure Display the "CC-Link IE TSN Configuration" window. [Navigation Window]  [Parameter]  [Module Information]  Model  [Basic Setting]  [Network Configuration Settings] Select the Main module of the FPGA modules from the "Module List" and drag and drop it onto the station list or network structure diagram.
Page 138 Write the set parameters to the CPU module of the master station and reset the CPU module of the master station, or turn off and on the power supply of the programmable controller. [Online]  [Write to PLC] Set the CPU module of the master station to RUN, and check that the DATA LINK LED of the FPGA module is turned on. 9 PARAMETER SETTING 9.2 For CC-Link IE TSN Communication Mode...
Page 139 Parameter setting Operating procedure Display the "CC-Link IE TSN Configuration" window. [Navigation Window]  [Parameter]  [Module Information]  Model  [Basic Setting]  [Network Configuration Settings] Double-click the FPGA module to start the FPGA Module Configuration Tool. All steps after step 3 are the same as in standalone mode. Page 129 For Standalone Mode 9 PARAMETER SETTING 9.2 For CC-Link IE TSN Communication Mode...
Page 140 MEMO 9 PARAMETER SETTING 9.2 For CC-Link IE TSN Communication Mode...
Page 141 PART 5 FPGAs This part consists of the following chapters. 10 FPGA DEVELOPMENT 11 FPGA INTERNAL CIRCUIT...
Page 142: Chapter 10 Fpga Development
FPGA DEVELOPMENT A sample circuit is written in the configuration ROM of the factory-shipped FPGA module. This chapter shows an example of changing the sample circuit. 10.1 FPGA Development Procedures The only block that requires to be developed (design/verification) is the user circuit block (uc2_top.v). Do not modify the circuit description of the standard circuit.
Page 143: Standard Circuit Block
Standard circuit block The configuration of the standard circuit block is shown below. Top part (top1) Timing generator Platform part (tg2_top) (pt2_top) Logging part (13) DDR3L SDRAM (lf2_top) I/O control block control part (dc3_top) selector DDR3L (is2_top) SDRAM Digital input control User circuit block Connector FIFO...
Page 144 Function block Function Timing generator (tg2_top.v) Generates input/output timing between the input/output control block and the user circuit block. The following four timing signals are generated. • Sampling pulse for digital input filter • Digital/analog data sampling pulse • Digital/analog data update pulse •...
Page 145: User Circuit Block
User circuit block The configuration of the user circuit block at the time of shipment from the factory is shown below. User circuit block (uc2_top) Digital signal Digital signal Digital output Digital input [15:0] [15:0] [101:0] Digital [101:0] [15:0] control part 0 control part 0 Digital signal[15:0] control part...
Page 146 When not modifying the user circuit block If the user circuit block is not modified, the configuration ROM can be used without modification. For usage examples, refer to the following. Page 298 FUNCTIONS Page 366 SAMPLE CIRCUIT IN STANDALONE MODE When developing the FPGA with a modified user circuit block The following products are required for FPGA development with a modified user circuit block.
Page 147: Fpga Design Procedures
10.2 FPGA Design Procedures When editing the user circuit block, change the RTL of the synthesis environment ($HOME\RTL\TOP\UC). For input/output (terminal list, timing) connected to the user circuit block, refer to the following. Page 218 Connection block list Page 610 List of User Circuit Block Terminals Page 220 Module common interface 10 FPGA DEVELOPMENT 10.2 FPGA Design Procedures...
Page 148: Fpga Verification Procedure
10.3 FPGA Verification Procedure Verification environment The verification environment for the sample circuit and the configuration of the verification environment are shown below. : Need to be changed according to the user circuit block, : Need to be changed according to the development environment, : Do not change TB_TOP.sv Data input...
Page 149 Directory Description Changeability $HOME  Simulation top folder    RTL storage directory   RTL storage directory (top layer)  RTL storage directory (UC) (user circuit block)  RTL storage directory (TOP, each block) (standard circuit)   vendormod Vendor model (outside the FPGA) storage directory ...
Page 150 FPGA development environment for the CC-Link IE TSN FPGA module. If there is any difference, store the file downloaded again from the Mitsubishi Electric FA site. After modifying the provided patterns stored in (12) FNx_TOP_XXXXXX.sv in the configuration of the verification environment, store them in the same location.
Page 151 Verification item Verification items for the provided patterns are shown below. Check the reference for details on the validation patterns. Validation pattern Item Verification item Reference name ■Purpose FNA_TOP_01010101 DC input/output Page 150 DC input/ check To perform inversion control and output control for the DC input of DC input/output circuit output check boards, and to check that it is output as the DC output of the DC input/output circuit boards...
Page 152 DC input/output check ■Validation pattern name FNA_TOP_01010101 ■Purpose To perform inversion control and output control for the DC input of DC input/output circuit boards, and to check that it is output as the DC output of the DC input/output circuit boards ■Check item Perform inversion control and output control for the DC input of DC input/output circuit boards, and check that it is output as the DC output of the DC input/output circuit boards.
Page 153 To check B0, set the register areas as shown in the table below. When setting the register areas, set b0 of Internal operation start/stop (mode_ctrl2) (FPGA register address: 1000_0002H) to Stop (0). When b0 is set to Stop (0), FPGA external reset (IOB0_RSTL, IOE_RSTL) becomes 0. When b0 is set to Start (1), FPGA external reset (IOB0_RSTL, IOE_RSTL) becomes 1.
Page 154 Differential input/output check ■Validation pattern name FNA_TOP_01010102 ■Purpose To perform inversion control and output control for the differential input of differential input/output circuit boards, and to check that it is output to the differential output of the differential input/output circuit boards ■Check item Perform inversion control and output control for the differential input of differential input/output circuit boards, and check that it is output to the differential output of the differential input/output circuit boards.
Page 155 To check B0, set the register areas as shown in the table below. Also set b0 of Write/read data control register (usr_wrdat_ctrl) (FPGA register address: 1000_A000H) to 1. Register name Setting value Reference Output signal/Input output direction signal selection (B0) 0003H Page 536 Select output signal or I/O (ioport_iob0_dio485_osel)
Page 156 Pulse output check ■Validation pattern name FNA_TOP_01010103 ■Purpose To check that the pulse output of the user circuit block is output to the differential output of differential input/output circuit boards ■Check item Check the operation of the pulse output of the user circuit block. (Circuit boards B0, B1, B2, E0, E1, and E2 connect to differential input/output circuit boards.) ■Procedure Configuration: B0 to B2 differential input/output circuit boards and E0 to E2 differential input/output circuit boards, without...
Page 157 Register name Setting Reference value Pulse output part pulse width upper limit value (lower side) (B0) (usr_wreg_110) 0003H Page 587 Pulse output part pulse width upper limit value Pulse output part pulse width upper limit value (upper side) (B0) (usr_wreg_111) 0000H Pulse output part pulse width upper limit value (lower side) (B1) (usr_wreg_115) 0003H...
Page 158 Register name Setting Reference value Pulse output part pulse output mask 0 (B0) (usr_wreg_142) FFFFH Page 590 Pulse output part pulse output mask Pulse output part pulse output mask 1 (B0) (usr_wreg_143) 0001H Pulse output part pulse output mask 0 (B1) (usr_wreg_144) FFFFH Pulse output part pulse output mask 1 (B1) (usr_wreg_145) 0001H...
Page 159 Counter operation check ■Validation pattern name FNA_TOP_01010104 ■Purpose To check that 32-bit ring counters (2-phase multiple of 4)/32-bit ring counters (1-phase multiple of 1) implemented in the user circuit block count against differential inputs from differential input/output circuit boards ■Check item Check the operation of 32-bit ring counters (2-phase multiple of 4)/32-bit ring counters (1-phase multiple of 1) in the user circuit block.
Page 160 Register name Setting Reference value Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower side) (B0) 0000H Page 594 Counter control part 32-bit (usr_wreg_189) ring counter (2-phase multiple of 4) preset data Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (upper side) (B0) 0000H (usr_wreg_18A) Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower side) (B1)
Page 161 Register name Setting Reference value Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction (B0) (usr_wreg_1A0) 0001H Page 595 Counter control part 32-bit ring counter (1-phase multiple of 1) Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction (B1) (usr_wreg_1A3) 0001H preset instruction Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction (B2) (usr_wreg_1A6)
Page 162 Register name Setting Reference value Counter control part 32-bit ring counter (1-phase multiple of 1) input signal selection (B0) 0403H Page 586 Counter control part 32-bit (usr_wreg_0D5) ring counter (1-phase multiple of 1) input signal selection Counter control part 32-bit ring counter (1-phase multiple of 1) input signal selection (B1) 0403H (usr_wreg_0DD) Counter control part 32-bit ring counter (1-phase multiple of 1) input signal selection (B2)
Page 163 Set b9 of Write/read data control register (usr_wrdat_ctrl) (FPGA register address: 1000_A000H) to 1. Read Counter control part 32-bit ring counter (2-phase multiple of 4) counter value (lower side) (B0) (usr_rreg_1B3) (FPGA register address: 1000_BB66H) to Counter control part 32-bit ring counter (2-phase multiple of 4) counter value (upper side) (E2) (usr_rreg_1BE) (FPGA register address: 1000_BB7CH) and Counter control part 32-bit ring counter (1- phase multiple of 1) counter value (lower side) (B0) (usr_rreg_1BF) (FPGA register address: 1000_BB7EH) and Counter control part 32-bit ring counter (1-phase multiple of 1) counter value (lower side) (E2) (usr_rreg_1CA) (FPGA register...
Page 164 Logging (non-time division mode) check ■Validation pattern name FNA_TOP_01010105 ■Purpose To check that the differential input of differential input/output circuit boards is logged to DDR3L SDRAM ■Check item Perform logging for the differential input of differential input/output circuit boards and 32-bit ring counters (2-phase multiple of 4), and check that data is logged to DDR3L SDRAM.
Page 165 Register name Setting Reference value Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B0) 0201H Page 584 Counter control part 32-bit (usr_wreg_0A5) ring counter (2-phase multiple of 4) input signal selection Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B1) 0403H (usr_wreg_0AD) Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B2)
Page 166 IOB0_X[0] 100ns 100ns cycle IOB0_X[1] IOB1_X[2] 200ns 200ns cycle IOB1_X[3] IOB2_X[4] 200 or 300ns 250ns cycle IOB2_X[5] IOE0_X[6] 400ns 400ns cycle IOE0_X[7] IOE1_X[1] 500ns 500ns cycle IOE1_X[4] IOE2_X[7] 1000ns 1000ns cycle IOE2_X[2] After 4s has elapsed, set b1 of Logging control part user logging control (usr_wreg_180) (FPGA register address: 1000_B300H) to 1, and b1 of Write/read data control register (usr_wrdat_ctrl) (FGA register address: 1000_A000H) to 1, and input the end trigger.
Page 167 Analog output check ■Validation pattern name FNA_TOP_01010106 ■Purpose To check that analog outputs (analog data, enable, LDAC) are performed according to the register settings of the user circuit block ■Check item Check that analog outputs (analog data, enable, LDAC) are performed according to the register settings of the user circuit block.
Page 168 Analog input and logging (time division mode) check ■Validation pattern name FNA_TOP_01010107 ■Purpose To check that the analog input of analog input/output circuit boards is logged to DDR3L SDRAM ■Check item Check that the analog input of analog input/output circuit boards is logged to DDR3L SDRAM in a time division manner. Logging is performed in trigger operation mode.
Page 169 After 8s has elapsed, read the register areas shown in the table below. Check that the expected values shown in the table below are read for the register areas. Register name Expected value Value Reference Logging state register (lgdw_sts) 0410H Page 551 Logging state register Logging system flag (lgdw_sys_sts) 0004H...
Page 170 Logging (automatic transfer mode) check ■Validation pattern name FNA_TOP_01010108 ■Purpose To check that logging can be performed normally when b0 of Logging control part automatic transfer mode setting (usr_wreg_095) (FPGA register address: 1000_B12AH) is set to Enable (1) ■Check item Check that, when b0 of Logging control part automatic transfer mode setting (usr_wreg_095) (FPGA register address: 1000_B12AH) is set to Enable (1), the logging enable signal (logging start) is output according to the logging control trigger and that data is written to DDR3L SDRAM normally.
Page 171 Register name Setting Reference value Logging control part sampling pulse signal selection (usr_wreg_093) 0002H Page 581 Logging control part sampling pulse signal selection Logging control part automatic transfer mode setting (usr_wreg_095) 0001H Page 582 Logging control part automatic transfer mode setting After the preprocessing of the internal operation start, start the internal operation.
Page 172 Verification details This section describes the tasks and parameters included in the provided patterns. Precautions • Since the firmware automatically controls the parts that use the private register to control the FPGA, set the public register according to the provided patterns. •...
Page 173 File name Task name Description inc/tb_common.sv task T_TIMFILSET( Set the normal timing register/filter register. Set the register corresponding to the slot int slt, number specified by slt. int mode, • slt: Specify a slot number. int dir=0); 0d: B0 1d: B1 2d: B2 3d: E0 4d: E1...
Page 174 File name Task name Description inc/board.sv task automatic T_ADC_SPI( Task for analog input/output circuit boards input bit[2:0] csl, Perform ADC SPI communication. input bit[15:0] sdi, • csl: Chip select number (0 to 2) input bit[15:0] do_0a = '0, • sdi: ADC serial data output input bit[15:0] do_0b = '0, •...
Page 175 ■Parameters included in provided patterns File name Parameter name Description inc/tb_common.sv parameter P_BSLT0 Determine the FPGA external connection (Connector (B0)). 0: No connection 1: DC input/output circuit board 2: Differential input/output circuit board 3 or greater: No connection The defparam statement is used to declare the connection in each pattern. inc/tb_common.sv parameter P_BSLT1 Determine the FPGA external connection (Connector (B1)).
Page 176: Fpga Logic Synthesis Procedures
10.4 FPGA Logic Synthesis Procedures Logic synthesis environment The logic synthesis environment for the provided sample circuit is shown below. Modify this environment and execute logic synthesis. : Need to be changed according to the user circuit block, : Do not change Directory Description Changeability...
Page 177 Check the difference between the */ file of (5) in the configuration for the logic synthesis environment and RTL of FPGA development environment for CC-Link IE TSN FPGA module. When the differences have been found, store the file that is re-downloaded from Mitsubishi Electric FA Global Website. Double-click "Compile Design" to execute the compilation on FPGA development software.
Page 178 ■Notes and restrictions The following table lists notes and restrictions when executing logic synthesis. Item Description Initial logic synthesis Execute logic synthesis using the provided logic synthesis environment and create a report file. The report file is created in the logic procedure synthesis environment (6) folder.
Page 179: Chapter 11 Fpga Internal Circuit
FPGA INTERNAL CIRCUIT The circuit mounted on the FPGA of the factory default FPGA module is shown below. 11.1 Overview The FPGA structure of the factory default FPGA module is shown below. The only block that needs development is the user circuit block (uc2_top.v).
Page 180 FPGA peripheral circuit connection The peripheral circuit connection of the FPGA is shown below. ■FPGA circuit board Intel Cyclone V 5CGXFC7D6F27I7N IOB0_X[0] Connector BUSCLK Micro- · CPU_A[29:1] computer CPU_CSL[0] IOB0_X[7] CPU_CSL[1] IOB0_XOEL[0] CPU_CSL[2] IOB0_XOEL[1] CPU_RDL CPU_WRSTBL IOB0_Y[0] CPU_WRL[1:0] · CPU_D[15:0] CPU_WAITL IOB0_Y[7] IOB0_YCK[0]...
Page 181 ■DC input/output circuit board DC input Connector Spring clamp circuit terminal block · Digital isolator CH15 Digital isolator DC output Digital isolator circuit CH1…CH6 Digital isolator CH9…CH14 CH15 Digital isolator 5V power supply monitoring Model identification 11 FPGA INTERNAL CIRCUIT 11.1 Overview...
Page 182 ■Differential input/output circuit board Connector Differential Spring clamp input circuit terminal block · Digital isolator · · Differential CH1…CH6 output circuit Digital isolator · · · Digital isolator Differential I/O circuit Digital isolator 5V power supply monitoring Model identification 11 FPGA INTERNAL CIRCUIT 11.1 Overview...
Page 183 ■Analog input/output circuit board Connector Digital isolator Spring clamp ADC circuit terminal block CH8-11 CH4-7 CH0-3 SCLK CONVST DOUTA DOUTB DOUTC DOUTD BUSY DAC circuit SCLK /SYNC /LDAC Analog power supply monitoring Model identification ■Prefix The prefix of an external terminal name is already determined for each connector. Terminal prefixes are shown below. Target connector Corresponding signal (prefix) Common from B0 to B2...
Page 184: Function Blocks
Function blocks Standard circuit Do not change the standard circuit. If the standard circuit is modified, the operation of various functions cannot be guaranteed. Top part (top1) Timing generator Platform part (tg2_top) (pt2_top) Logging part (13) DDR3L SDRAM (lf2_top) I/O control block control part (dc3_top) selector...
Page 185 Module specific circuit Page 196 Digital input control part (di2_top) part block) in the level immediately below. The digital input control part • NZ2GN2S-D41P01 implements the following functions. • NZ2GN2S-D41D01 • Digital filter function • NZ2GN2S- • Outputs the signal after digital filtering to the register block and user...
Page 186 User circuit block (sample circuit) The structure of the factory default user circuit block (sample circuit) is shown below. User circuit block (uc2_top) Digital signal Digital signal Digital output Digital input [15:0] [15:0] [101:0] Digital [101:0] [15:0] control part 0 control part 0 Digital signal[15:0] control part...
Page 187: Reset System Diagram
Reset system diagram The reset system diagram is shown below. Top part (top1) Platform part (pt2_top) Timing generator (tg2_top) Logging part DDR3L SDRAM (lf2_top) (13) control part (dc3_top) I/O control block DDR3L selector SDRAM (is2_top) Digital input control Connector User circuit FIFO part (di2_top) block...
Page 188: Clock System Diagram
Clock system diagram The clock system diagram is shown below. Top part (top1) Platform part (pt2_top) Timing generator (tg2_top) Logging part (13) DDR3L SDRAM (lf2_top) control part I/O control block (dc3_top) DDR3L selector SDRAM (is2_top) Digital input control User circuit Connector Connector FIFO...
Page 189: Details
The module specific circuit used for each module is shown below. Module category Model Connection circuit board Target input/output control part block Main module NZ2GN2S-D41P01 B0, B1, B2: DC input/output circuit board Digital input control part (di2_top) Digital output control part (do2_top) NZ2GN2S-D41D01 B0, B1, B2: Differential input/output circuit...
Page 190: Standard Circuit
11.3 Standard Circuit Do not change the standard circuit. If the standard circuit is modified, the operation of various functions cannot be guaranteed. Module common circuit Reset control part (rc2_top) All register areas inside the FPGA are reset by a reset (RSTL) input from the MCU until the state transition of the FPGA or module is established, such as during configuration.
Page 191 ■Reset target list The reset target list is shown below. Reset cause Reset function Reset (RSTL) Sets all FPGA register areas until the FPGA circuit is established. • Initializing at power-on • Configurating Internal operation start/stop Shows the processing content of each block as below when internal operation start/stop is stop. ■Timing generator •...
Page 192 Platform part (pt2_top) The platform part is a block that implements IP using Platform Designer included in the FPGA design software. This circuit performs FPGA internal register access from the MCU and DDR3L SDRAM access from the logging module. Top part (top1) Platform part (pt2_top) DDR3L DDR3L SDRAM...
Page 193 Logging part (lf2_top) It temporarily saves the time information and logging data output from the user circuit block in a buffer (FIFO 64-bit  16 levels) for each logging cycle timing pulse of the timing generator output. Then, they are written to DDR3L SDRAM. Logging starts with a signal that is selected as the logging start signal for the user circuit block or register part according to the setting value of the logging operation control register [12].
Page 194 ■Timing chart Logging starts when the internal operation start/stop is Start and the logging start signal (logging start (register part), signal with logging enable selected) is Start (1). After logging starts, when the logging cycle timing (logging cycle timing, signal with user sampling pulse selected) is enabled (1), the DDR3L SDRAM address is generated and the logging data and time information are written to the DDR3L SDRAM.
Page 195 Timing generator (tg2_top) After setting internal operation start/stop to Start (1), this block generates the timing pulse used in each function block. A list of timing pulses used in each block is shown below. Item Connection destination Signal name Description Remarks Filter sampling pulse •...
Page 196 Input/output selector (is2_top) Each connector is connected to one of the following. • DC input/output circuit board • Differential input/output circuit board • Analog input/output circuit board The connector determines the circuit board based on the connected module type (IOB0_UNIT, IOB1_UNIT, IOB2_UNIT, IOE_UNIT).
Page 197 Register part (re2_top) This block notifies the setting values inside the FPGA via the platform part from the MCU. Top part (top1) User circuit register control area Always write register write data Microcom- Platform part Register part User circuit part connection connection (transient area)
Page 198: Module Specific Circuit (Nz2Gn2S-D41P01)
Module specific circuit (NZ2GN2S-D41P01) Digital input control part (di2_top) The input signal from the input/output selector is loaded into the digital input control part. For the DC input circuit board, the 16-bit digital signal is multiplexed into the lower 8 bits and the upper 8 bits on the DC input/ output circuit board, and loaded in units of 8 bits into the digital input control part.
Page 199 ■Monitor register For the monitor register of the digital input control part, refer to the following. Page 504 Digital input control part ■Digital filter A conceptual diagram of a digital filter is shown below. For the filter time, the input filter counter upper limit (IOB/E_X) and filter sampling pulse (B/E) can be set.
Page 200 ■Timing chart The selection of the timing pulse of the digital filter differs between the DC input/output circuit board and the differential input/ output circuit board. The DC input/output circuit board performs digital filtering in synchronization with the data sampling timing. The differential input/output circuit board sets the filter sampling pulse, generates the timing pulse, and implements the digital filter.
Page 201 Digital output control part (do2_top) A digital signal in the user circuit block or register part is selected by output signal selection register, and the digital signal is output to the outside of the FPGA via the input/output selector. The output timing is synchronized with the timing pulse signal from the timing generator.
Page 202 Item Operation Remarks HOLD/CLEAR function ■HOLD/CLEAR circuit HOLD/CLEAR for the DC input/output circuit board sets the By the register setting, HOLD/CLEAR is executed when the internal external reset ON/OFF setting. operation stops. The HOLD/CLEAR processing for each circuit HOLD/CLEAR for differential input/output circuit board sets board is shown below.
Page 203 ■Monitor register For the monitor register of the digital output control part, refer to the following. Page 506 Digital output control part ■Operation The output timing of the digital output control part varies depending on the DC input/output circuit board and the differential input/output circuit board.
Page 204: Module Specific Circuit (Nz2Gn2S-D41D01)
Module specific circuit (NZ2GN2S-D41D01) Digital input control part (di2_top) Same as NZ2GN2S-D41P01 ( Page 196 Digital input control part (di2_top)) Digital output control part (do2_top) Same as NZ2GN2S-D41P01 ( Page 199 Digital output control part (do2_top)) Digital input/output control part (dio2_top) Controls the bi-directional buffer when a differential input/output circuit board is connected.
Page 205 ■List of monitor register areas Register name Connection signal name I/O signal monitor (IOB0_DIO485)B0) (ioport_iob0_dio485_monitor) dio_iob0_dio485_i_clk100m_reg dio_iob0_dio485_o_clk100m_reg dio_iob0_dio485_en_clk100m_reg I/O signal monitor (IOB1_DIO485)B1) (ioport_iob1_dio485_monitor) dio_iob1_dio485_i_clk100m_reg dio_iob1_dio485_o_clk100m_reg dio_iob1_dio485_en_clk100m_reg I/O signal monitor (IOB2_DIO485)B2) (ioport_iob2_dio485_monitor) dio_iob2_dio485_i_clk100m_reg dio_iob2_dio485_o_clk100m_reg dio_iob2_dio485_en_clk100m_reg I/O signal monitor (IOE0_DIO485)E0) (ioport_ioe0_dio485_monitor) dio_ioe0_dio485_i_clk100m_reg dio_ioe0_dio485_o_clk100m_reg dio_ioe0_dio485_en_clk100m_reg I/O signal monitor (IOE1_DIO485)E1) (ioport_ioe1_dio485_monitor)
Page 206: Module Specific Circuit (Nz2Gn2S-D41Pd02)
Module specific circuit (NZ2GN2S-D41PD02) Digital input control part (di2_top) Same as NZ2GN2S-D41P01 ( Page 196 Digital input control part (di2_top)) Digital output control part (do2_top) Same as NZ2GN2S-D41P01 ( Page 199 Digital output control part (do2_top)) Digital input/output control part (dio2_top) Same as NZ2GN2S-D41D01 (...
Page 207: Module Specific Circuit (Nz2Ex2S-D41A01)
Module specific circuit (NZ2EX2S-D41A01) Analog input control part (ai2_top) When E0 to E2 are analog input/output circuit boards, it controls the ADC (three elements on one circuit board). Communication with the ADC uses SPI (Serial Peripheral Interface). In addition, the serial clock output and serial data output signals are common and the chip select signal is used to control ADC0 to ADC2 individually.
Page 208 ■Monitor register For information on the monitor register of the analog input control part, refer to the following. Page 507 Analog input control part ■Process The analog input control part performs the following processing. FPGA control start processing "A/D conversion enable/disable setting" (aiport_ad_start[2:0]) is temporarily saved in the RAM of the microcomputer. A/D conversion enable/disable setting value acquisition "A/D conversion enable/disable setting"...
Page 209 ■Operation The analog input control part performs the ADC register settings, ADC register initialization and ADC register setting end, and A/D conversion processing that reads A/D conversion values from the ADC. ADC register initialization and ADC register setting end set register areas in the ADC when the internal operation start/stop is Start and A/D conversion enable/disable setting is set to Enable (1).
Page 210 ■Configurable functions The configurable functions of the ADC are shown below. • Oversampling function • Offset function ■Oversampling function The ADC oversampling function performs digital averaging. Digitally averaging applies to the amount equal to the number of times set in "ADC oversampling ratio setting". Therefore, the falling edge timing of the IOE0 to E2_AD_BUSY signals is delayed by the amount of time to execute digital averaging.
Page 211 ■Offset function Offset errors caused by external factors of ADC can be compensated by the ADC offset value for each channel. Regarding the ADC offset setting value CH0 to 1 (E0) (aiport_ade0_0-1_offset) (FPGA register address: 1000_6160H) to ADC offset setting value CHA to B (E2) (aiport_ade2_a-b_offset) (FPGA register address: 1000_6182H), depending on their settings, up to 128 resolutions can be automatically added or subtracted for each channel.
Page 212 ■I/O conversion characteristics using the offset function The I/O conversion characteristics using the offset function are shown below. Slope characteristics and scaling are not possible with the standard circuit. Add them in the user circuit block if necessary. Use them within the practical analog input range. If a value is out of the range, the maximum resolution and accuracy may not fall within the range of performance specifications.
Page 213 Analog output control part (ao2_top) If E0 to E2 are analog input/output circuit boards, it controls the DAC (two elements on one circuit board). Communication with the DAC uses SPI (Serial Peripheral Interface). In addition, the serial clock output, serial data output signal, and chip select signal are common, and an address (2 bits) for each chip is used to control the DAC individually.
Page 214 ■Processing flow The processing flow of the analog output control part is shown below. From the MCU, set the analog output control part register mounted on the FPGA. After setting the analog output control register, transfer the D/A conversion value to the DAC at each data update timing cycle.
Page 215 ■Operation The analog output control part performs D/A conversion processing to transfer the D/A conversion value to the DAC. The analog output control part register setting is performed by firmware. After analog output control part register setting end, follow the analog output control register ("Select D/A conversion value" (aoport_da_data_sel), "Select D/A conversion timing" (aoport_da_cyc_sel), and "Select DAC LDAC signal"...
Page 216 ■Offset function Offset errors caused by external factors of DAC can be compensated by the DAC offset value for each channel. DAC offset channel (E)(remote buffer memory address: 0601H, 0605H, 0609H, 060DH, 0611H, 0615H), setting it can automatically add or subtract up to 32768 resolutions for each channel. The resolution for the DAC output voltage range is shown below.
Page 217 ■I/O conversion characteristics using the offset function The I/O conversion characteristics using the offset function are shown below. -9.9 32768 65207 65535 digit digit: D/A conversion value V: Analog output voltage (1) Offset value (2) If the digital input for D/A conversion + DAC offset value > 65535 digits, it varies in the range of 10 to 15V. (a) Analog output practical range 11 FPGA INTERNAL CIRCUIT 11.3 Standard Circuit...
Page 218: Notes And Restrictions
Notes and restrictions Notes and restrictions for the standard circuit are shown below. • Set "Data sampling timing" and "Filter sampling pulse" to be the same. • Stop the logging operation before accessing DDR3L SDRAM from the MCU. • Enable logging start after performing all necessary settings such as the operation of the timing generator. •...
Page 219: User Circuit Block
11.4 User Circuit Block The user circuit block is a block written in RTL according to the application. This section describes the following. • Connection block list • Terminal list • Interface specification • Circuit implemented in the sample circuit provided When creating a new user circuit block, or when partially or completely reusing it, refer to the following and perform the development.
Page 220 Connection block list Blocks connected to the input/output selector are enabled or disabled depending on the model. The connected blocks are shown below. • Digital input control part • Digital output control part • Digital input/output control part • Analog input control part •...
Page 221 Model Module Connection circuit board Effective block category NZ2GN2S-D41P01 Main module B0, B1, B2: DC input/output circuit u_di2_top_b0, u_di2_top_b1, u_di2_top_b2, u_do2_top_b0, board u_do2_top_b1, u_do2_top_b2 NZ2GN2S-D41D01 B0, B1, B2: Differential input/output u_di2_top_b0, u_di2_top_b1, u_di2_top_b2, u_do2_top_b0, circuit board u_do2_top_b1, u_do2_top_b2, u_dio2_top_b0, u_dio2_top_b1,...
Page 222: Module Common Interface
Module common interface Logging control (output) The timing chart when using the logging control (output) is shown below. If the FPGA register is set as follows: FPGA register Setting Remarks value Logging cycle timing (tim_log_cyc) (FPGA register address: 1000_2200H) 0001H 1s Logging data size setting (lgdw_area)(FPGA register address: 1000_9008H) 256 records (16kB)
Page 223 If the user sampling pulse (uc_loguserpulse_clk100m_reg) is smaller than the minimum setting value of the logging cycle timing below, it will not work properly. ( Page 193 Timing generator (tg2_top)) After enabling (1) the user sampling pulse (uc_loguserpulse_clk100m_reg), logging processing is performed in the logging part.
Page 224 ■Automatic transfer mode The logging control operates using the automatic transfer mode of the logging part. In the automatic transfer mode, logging start (user circuit block) needs to be output according to the logging control trigger input to the user circuit block. If b3 of the logging operation control register (lgdw_ctrl) (FPGA register address: 1000_9000H) is set to Rising for logging start allowed (1), the rising edge of logging start (user circuit block) is detected and logging starts.
Page 225 • Automatic transfer mode (normal operation) [Common to user circuit block logging part] Logging control trigger Falling edge enable Rising edge enable Rising edge enable Falling edge enable Falling edge enable re_rs_lgdw_ctrl_3_clk100m_reg [User circuit block] Logging data Logging data Logging data Logging data uc_logdat_clk100m_reg[431:0] Logging end trigger...
Page 226 • Automatic transfer mode (faulty operation) [Common to user circuit block logging part] Logging control trigger Falling edge enable Falling edge enable Rising edge enable Rising edge Rising edge enable Rising edge enable re_rs_lgdw_ctrl_3_clk100m_reg enable [User circuit block] Logging data Logging data Logging data Logging data...
Page 227: Nz2Gn2S-D41P01, Nz2Gn2S-D41Pd02, Nz2Ex2S-D41P01
NZ2GN2S-D41P01, NZ2GN2S-D41PD02, NZ2EX2S-D41P01 DC input/output circuit board (input) The user circuit block timing chart when using the DC input/output circuit board is shown below. In addition, the setting values of the digital input control part in this timing chart are shown below.
Page 228 DC input/output circuit board (output) The user circuit block timing chart when using the DC input/output circuit board (output) is shown below. The setting values of the digital output control part in this timing chart are shown below. Target register Setting Remarks value...
Page 229 ■Timing chart (HOLD) example clk100m [User circuit block] Digital output signal D1[15:0] D2[15:0] D3[15:0] uc_iob0_y_clk100m_reg[15:0] [Digital output control part] Data update timing tg_dataout_tmgpulse_0_clk100m_1shot_reg Internal operation start/stop re_rd_mode_ctrl2_clk100m_reg External reset ON/OFF setting (I) H re_rs_ioport_set_0_clk100m_reg Output signal selection (B0) (I) H re_rs_oport_iob0y_osel_clk100m_reg Output value setting register D4[15:0]...
Page 230: Nz2Gn2S-D41D01, Nz2Gn2S-D41Pd02, Nz2Ex2S-D41D01
NZ2GN2S-D41D01, NZ2GN2S-D41PD02, NZ2EX2S-D41D01 Differential input/output circuit board (input) The user circuit timing chart when using the differential input/output circuit board is shown below. In addition, the setting values of the digital input control part in this timing chart are shown below. Target register Setting Remarks...
Page 231 Differential input/output circuit board (output) The user circuit block timing chart when using the differential input/output circuit board (output) is shown below. The setting values of the digital output control part in this timing chart are shown below. Target register Setting Remarks value...
Page 232 ■Timing chart (HOLD/CLEAR) example clk100m [User circuit block] Digital output signal D1[15:0] D2[15:0] D3[15:0] uc_iob0_y_clk100m_reg[15:0] [Digital output control part] Data update timing (I) L tg_dataout_tmgpulse_0_clk100m_1shot_reg Internal operation start/stop re_rd_mode_ctrl2_clk100m_reg Differential output HOLD/CLEAR (B0) [1:0] CLEAR setting (00b, 01b) re_rs_oport_iob1y_holdclr_15_0_clk100m_reg[1:0] Output signal selection (B0) (I) H re_rs_oport_iob0y_osel_clk100m_reg Output value setting register...
Page 233: Nz2Ex2S-D41A01
NZ2EX2S-D41A01 Analog input/output circuit board (input) The user circuit block timing chart when using the analog input/output circuit board is shown below. The setting values for the analog input control part in this timing chart are shown below. Target register Setting Remarks value...
Page 234 ■Timing chart example 4μs Data sampling pulse (Internal) tg_sampling_tmgpulse_x_clk100m_1shot_reg [Analog input control part] IOE0_X0 (External terminal output) (IOE0_CONVST) IOE0_X7 (External terminal input) (IOE0_AD_BUSY) IOE0_X1 (External terminal output) (IOE0_AD_CSL[0]) IOE0_XOEL0 (External terminal input) (IOE0_AD0_DOUTA) current input voltage input current input voltage input IOE0_XOEL1 (External terminal input) (IOE0_AD0_DOUTB)
Page 235 Analog input/output circuit board (output) The user circuit block timing chart when using the analog input/output circuit board (output) is shown below. Also, the setting values of the analog output control part in this timing chart are shown below. Target register Setting Remarks value...
Page 236 Description Sets the output data to D/A conversion value CH0 (E0) (uc_ioe0_andat_clk100m_reg[15:0]), D/A conversion value CH1 (E0) (uc_ioe0_andat_clk100m_reg[31:16]), and D/A conversion value enable (E0) (uc_ioe0_andat_en_clk100m_reg) to Enable (1). Set D/A conversion value enable (E0) (uc_ioe0_andat_en_clk100m_reg) to Enable(1) when synchronizing between DAC channels, and, after 5.70s, sets LDAC output CH0-1 (E0) (uc_ioe0_ldac_clk100m_reg) to enable (0) for 300ns.
Page 237: If Specification Notes/Restrictions
IF specification notes/restrictions The user circuit IF specification notes/restrictions are shown below. Description Input/output (input/output declarations inside the RTL, input/output signal names) of the user circuit (uc2_top.v) must not be changed. Set terminals that are not used as input OPEN/output non-dominant fixed. The logging target is 512 bits, but the time information (80 bits) is given in the logging part.
Page 238 Operation when pulse interval constraint is violated ■For user circuit data sampling pulse 4μs or less User circuit data sampling pulse Analog input control part A/D conversion processing A/D conversion processing (1) The user circuit data sampling pulse is ignored because A/D conversion processing is in progress. ■For user circuit D/A conversion value enable 6μs or less User circuit D/A conversion...
Page 239 Reset sequence CLKIN_SYS clk100m (Internal) PLL lock period H/W reset (I) L RSTL PLL lock signal (I) L PLL_LOCK H/W reset (for PLL) (O) L 2-stage FF + SR-FF rst_hw_n (CLKIN_SYS) System reset (O) L 5clk rst_n (clk100m) DDR3L SDRAM (Internal) Resetting Calibrating...
Page 240: Sample Circuit
Sample circuit Sample circuit operation details Sample circuit user circuit block diagram is shown below. Also, the register connections (1) to (6) are shown below. ■Block Diagram User circuit part (uc2_top) × Digital control part (uc3_dig_top) Ò (11) (10) Ø Pulse output part (uc3_plsout_top) Ó...
Page 241 Function Description classification  Digital control part Implements the following for the digital signal input from the digital input control part. (uc3_dig_top) • Inversion process When the "Digital control part enable/disable control register (IOB0_X0 B0) [1]" is set to Enable (1), the digital signal is inverted and output.
Page 242 *1 Only CH0 is explained. The same functions are implemented for number of channels for each circuit board. The number of channels to implement multiple is shown below. Function Number of Breakdown name channels Digital input/output (DC input/output circuit board/differential input/output circuit board): 6 circuit boards  16 Digital control 102CH part...
Page 243 ■User circuit block diagram connection list Block diagram No. Connection signal name Register address  re_rs_usr_wreg_000_clk100m_reg[1:0] 1000_B000H  re_rs_usr_wreg_001_clk100m_reg[1:0] 1000_B002H  re_rs_usr_wreg_002_clk100m_reg[1:0] 1000_B004H  re_rs_usr_wreg_003_clk100m_reg[1:0] 1000_B006H  re_rs_usr_wreg_004_clk100m_reg[1:0] 1000_B008H  re_rs_usr_wreg_005_clk100m_reg[1:0] 1000_B00AH  re_rs_usr_wreg_006_clk100m_reg[1:0] 1000_B00CH  re_rs_usr_wreg_007_clk100m_reg[1:0] 1000_B00EH  re_rs_usr_wreg_008_clk100m_reg[1:0] 1000_B010H ...
Page 244 Block diagram No. Connection signal name Register address  re_rs_usr_wreg_03f_clk100m_reg[1:0] 1000_B07EH  re_rs_usr_wreg_040_clk100m_reg[1:0] 1000_B080H  re_rs_usr_wreg_041_clk100m_reg[1:0] 1000_B082H  re_rs_usr_wreg_042_clk100m_reg[1:0] 1000_B084H  re_rs_usr_wreg_043_clk100m_reg[1:0] 1000_B086H  re_rs_usr_wreg_044_clk100m_reg[1:0] 1000_B088H  re_rs_usr_wreg_045_clk100m_reg[1:0] 1000_B08AH  re_rs_usr_wreg_046_clk100m_reg[1:0] 1000_B08CH  re_rs_usr_wreg_047_clk100m_reg[1:0] 1000_B08EH  re_rs_usr_wreg_048_clk100m_reg[1:0] 1000_B090H  re_rs_usr_wreg_049_clk100m_reg[1:0] 1000_B092H ...
Page 245 Block diagram No. Connection signal name Register address  re_rs_usr_wreg_093_clk100m_reg[6:0] 1000_B126H  re_rs_usr_wreg_094_clk100m_reg[0] 1000_B128H  re_rs_usr_wreg_095_clk100m_reg[0] 1000_B12AH  re_rs_usr_wreg_0a3_clk100m_reg[15:0] 1000_B146H  re_rs_usr_wreg_0a4_clk100m_reg[15:0] 1000_B148H  re_rs_usr_wreg_0a5_clk100m_reg[5:0] 1000_B14AH  re_rs_usr_wreg_0a5_clk100m_reg[13:8] 1000_B14AH  re_rs_usr_wreg_0ab_clk100m_reg[15:0] 1000_B156H  re_rs_usr_wreg_0ac_clk100m_reg[15:0] 1000_B158H  re_rs_usr_wreg_0ad_clk100m_reg[5:0] 1000_B15AH  re_rs_usr_wreg_0ad_clk100m_reg[13:8] 1000_B15AH ...
Page 246 Block diagram No. Connection signal name Register address  re_rs_usr_wreg_112_clk100m_reg[15:0] 1000_B224H  re_rs_usr_wreg_113_clk100m_reg[15:0] 1000_B226H  re_rs_usr_wreg_115_clk100m_reg[15:0] 1000_B22AH  re_rs_usr_wreg_116_clk100m_reg[15:0] 1000_B22CH  re_rs_usr_wreg_117_clk100m_reg[15:0] 1000_B22EH  re_rs_usr_wreg_118_clk100m_reg[15:0] 1000_B230H  re_rs_usr_wreg_11a_clk100m_reg[15:0] 1000_B234H  re_rs_usr_wreg_11b_clk100m_reg[15:0] 1000_B236H  re_rs_usr_wreg_11c_clk100m_reg[15:0] 1000_B238H  re_rs_usr_wreg_11d_clk100m_reg[15:0] 1000_B23AH  re_rs_usr_wreg_11f_clk100m_reg[15:0] 1000_B23EH ...
Page 247 Block diagram No. Connection signal name Register address  re_rs_usr_wreg_168_clk100m_reg[0] 1000_B2D0H  re_rs_usr_wreg_180_clk100m_reg[1:0] 1000_B300H  re_rs_usr_wreg_181_clk100m_reg[0] 1000_B302H  re_rs_usr_wreg_188_clk100m_reg[0] 1000_B310H  re_rs_usr_wreg_189_clk100m_reg[15:0] 1000_B312H  re_rs_usr_wreg_18a_clk100m_reg[15:0] 1000_B314H  re_rs_usr_wreg_18b_clk100m_reg[0] 1000_B316H  re_rs_usr_wreg_18c_clk100m_reg[15:0] 1000_B318H  re_rs_usr_wreg_18d_clk100m_reg[15:0] 1000_B31AH  re_rs_usr_wreg_18e_clk100m_reg[0] 1000_B31CH  re_rs_usr_wreg_18f_clk100m_reg[15:0] 1000_B31EH ...
Page 248 Clock system The user circuit clock is a single system clock (clk100m). Reset system The reset system diagram of the user circuit is shown below. Top part (top1) User circuit block (uc2_top) rst_n usr_rst_n Reset control All FFs (rc2_top) re_rd_mode_ctrl2_0_clk100m_reg Register part (re2_top) As shown in the diagram, two resets are input.
Page 249 ■Digital control part function list Function Overview Remarks  Inversion process Inverts the digital input signal (after filtering) and outputs it to Digital output enable/disable control. When "Digital control part enable/disable control register (IOB0_X0 B0)" [1] is set to Enable (1), the digital input signal (after filtering) is inverted. If it is set to Disable (0), through output occurs at Digital output enable/disable control.
Page 250 Signal name Logic Function Connection Initial Pulse destination value signal dig_iob2_y_clk100m_reg [15:0]  Digital output signal (B2 after digital control) Logging 0000h  control part, output block part   dig_ioe0_y_clk100m_reg [15:0] Digital output signal (E0 after digital control) Logging 0000h control part, output block...
Page 251 Pulse output part (uc3_plsout) This module sets the pulse width and the pulse output count, and outputs 0, 90, 180, and 270 degree pulses with a constant cycle. The block diagram, function list, and terminal list of the pulse output part are shown below. ■Pulse output part block diagram Pulse output part (uc3_plsout)* Pulse output part pulse width upper limit value...
Page 252 ■Pulse output part terminal list Signal name Logic Function Connection Initial Pulse destination value signal    clk100m System clock cc2_top  usr_rst_n Reset for user circuit (the AND between uc2_top reset and internal operation start/stop)   re_rs_usr_wreg_110_clk100m_reg[15:0] Pulse output part pulse width upper limit re2_top 0000h...
Page 253 Signal name Logic Function Connection Initial Pulse destination value signal re_rs_usr_wreg_130_clk100m_reg[15:0]  Pulse output part pulse output selection 0 re2_top 0000h  (B0)   re_rs_usr_wreg_131_clk100m_reg[15:0] Pulse output part pulse output selection 1 re2_top 0000h (B0)   re_rs_usr_wreg_132_clk100m_reg[1:0] Pulse output part pulse output selection 2 re2_top (B0) ...
Page 254 Signal name Logic Function Connection Initial Pulse destination value signal pls_iob1_plscnt_clk100m_reg[31:0]  Number of pulse outputs (B1) Output block 0000_0000h  part   pls_iob2_y_clk100m_reg[15:0] Pulse output (B2) Output block 0000h part   pls_iob2_y_dio485_clk100m_reg Pulse output (digital input/output) (B2) Output block part ...
Page 255 Reference enable generation The reference enable generator implements a 32-bit ring counter with the upper limit of "Pulse output part pulse width upper limit value (lower side)/(upper side) (B0)", and outputs the 0-degree enable pulse (pls_0degree_en) for pulse generation and 90-degree enable pulse (pls_90degree_en).
Page 256 ■Pulse output: Enable generation 0-degree enable (pls_0degree_en) and 90 degree enable (pls_90degree_en) are generated and output from the value of the pulse output reference counter (pls_base_counter_clk100m_reg). The truth values for pulse output enable generation are shown below. usr_rst_n 0 degree enable 90 degree enable (pls_0degree_en) (pls_90degree_en)
Page 257 ■Pulse output: Pulse generation timing chart clk100m Pulse output part pulse output enable (B0) re_rs_usr_wreg_1b8_clk100m_reg[15:0] Pulse output part pulse width upper limit value (lower side)/(upper side) (B0) {re_rs_usr_wreg_111_clk100m_reg[15:0], re_rs_usr_wreg_110_clk100m_reg[15:0]} Reference counter for pulse generation (Internal) 2d 3d 2d 3d 2d 3d 2d 3d 2d 3d Pulse generation enable (0 degrees)
Page 258 Counter control part (uc3_cnt_top) This module implements a counter controlled by digital signals input from the digital input control part. The counter implements a 32-bit ring counter (2-phase multiple of 4) and a 32-bit ring counter (1-phase multiple of 1). The block diagram, function list, and terminal list of the counter control part block are shown below.
Page 259 ■Counter control part function list Function Overview Remarks  Phase A and Phase B input selection From the digital input signal (B0 after filtering)/(digital input/output B0 after filtering) signal function (2-phase multiple of 4) (17 bits), "Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B0)"...
Page 260 Signal name Logic Function Connection Initial Pulse destination value signal re_rs_usr_wreg_0a5_clk100m_reg[12:8]  Counter control part 32-bit ring counter (2- re2_top  phase multiple of 4) input signal selection (B0) Phase B input selection   re_rs_usr_wreg_0a5_clk100m_reg[5] Counter control part 32-bit ring counter (2- re2_top phase multiple of 4) input signal selection (B0) Phase A register input...
Page 261 Signal name Logic Function Connection Initial Pulse destination value signal re_rs_usr_wreg_192_clk100m_reg[15:0]  Counter control part 32-bit ring counter (2- re2_top 0000h  phase multiple of 4) preset data (lower side) (E0)   re_rs_usr_wreg_193_clk100m_reg[15:0] Counter control part 32-bit ring counter (2- re2_top 0000h phase multiple of 4) preset data (upper side)
Page 262 Signal name Logic Function Connection Initial Pulse destination value signal re_rs_usr_wreg_0cc_clk100m_reg[15:0]  Counter control part 32-bit ring counter (2- re2_top 0000h  phase multiple of 4) counter upper limit value (upper side) (E2)   re_rs_usr_wreg_0cd_clk100m_reg [4:0] Counter control part 32-bit ring counter (2- re2_top phase multiple of 4) input signal selection (E2) Phase A input selection...
Page 263 Signal name Logic Function Connection Initial Pulse destination value signal re_rs_usr_wreg_0dd_clk100m_reg[5]  Counter control part 32-bit ring counter (1- re2_top  phase multiple of 1) input signal selection (B1) Phase A register input   re_rs_usr_wreg_0dd_clk100m_reg[13] Counter control part 32-bit ring counter (1- re2_top phase multiple of 1) input signal selection (B1) Phase Z register input...
Page 264 Signal name Logic Function Connection Initial Pulse destination value signal re_rs_usr_wreg_1ae_clk100m_reg[15:0]  Counter control part 32-bit ring counter (1- re2_top 0000h  phase multiple of 1) preset data (upper side) (E1)   re_rs_usr_wreg_0f3_clk100m_reg[15:0] Counter control part 32-bit ring counter (1- re2_top 0000h phase multiple of 1) counter upper limit value...
Page 265 Signal name Logic Function Connection Initial Pulse destination value signal cnt_ioe0_32ring_1pha1multi_counter_clk1  32-bit ring counter (1-phase multiple of 1) Output block 0000_0000h  00m_reg [31:0] counter value (E0) part   cnt_ioe1_32ring_2pha4multi_counter_clk1 32-bit ring counter (2-phase multiple of 4) Output block 0000_0000h 00m_reg [31:0] counter value (E1)
Page 266 ■Counter control (32-bit ring counter (2-phase multiple of 4)) It detects the rising edge and falling edge of Phase A and Phase B, and outputs the counter UP and DOWN signals in one pulse (clk100m). The truth table of the UP output and DOWN output is shown below. usr_rst_n clk100m Phase A...
Page 267 Pulse generator (uc3_pls_top) This module generates the sampling pulse for use in the logging control part, from the 0.5s sampling pulse for user circuit which is input from the timing generator. The block diagram, function list, and terminal list of the pulse generator are shown below.
Page 268 ■Counter (0.5s) Implements a 16-bit ring counter that counts up with the 0.5s sampling pulse (tg_05us_tmgpulse_clk100m_1shot_reg) for user circuit. The upper limit of the counter is fixed at 0001H and count up is done at every 0.5s. The truth value of the counter (0.5s) is shown below.
Page 269 ■Analog output control part function list Function Overview Remarks  D/A conversion D/A conversion value CH0/CH1 (E0) is generated by MCU system error notification and Analog output part value HOLD/CLEAR. The output combinations of D/A conversion values CH0/CH1 (E0) are shown below. generation •...
Page 270 ■Analog output part terminal list Module signal name Logic Function Connection Initial Pulse signal destination value    clk100m System clock cc2_top  usr_rst_n Reset for user circuit (the AND uc2_top between reset and internal operation start/stop) re_rs_usr_wreg_1c0_clk100m_reg[15:0]  Analog output part D/A conversion re2_top 0000h...
Page 271 ■Analog output part schematic timing chart clk100m Internal operation start/stop Analog output part D/A conversion value CH0/CH1 (E0) re_rs_usr_wreg_1c0_clk100m_reg[15:0], 0000_1111H 0000_1111H re_rs_usr_wreg_1c1_clk100m_reg[15:0] D/A conversion value CH0 (E0) 1111H 1111H uc_ioe0_andat_clk100m_reg[15:0] D/A conversion value CH1 (E0) 0000H 0000H uc_ioe0_andat_clk100m_reg[31:16] Analog output part D/A conversion value enable re_rs_usr_wreg_1c6_clk100m_reg[0] Analog output start pulse (Internal)
Page 272 ■D/A conversion value generation In D/A conversion value generation, D/A conversion value is generated by "Analog output part HOLD/CLEAR", "Microcomputer system error notification", and "Analog output part D/A conversion value CH0/CH1 (E0)". The truth table for D/A conversion value generation is shown below. usr_rst_n clk100m MCU system error...
Page 273 Logging control part (uc3_log_top) This module provides the logging control part with logging data (logging target data), logging enable (logging start signal), logging end trigger (logging end pulse during trigger operation mode), and user sampling pulse (logging data sampling). The block diagram, function list, and terminal list of the logging control part are shown below.
Page 274 Function Description Logging enable Logging enable Selects logging enable (logging start) in the logging control part and then outputs it. 1 bit is selected and output selector selection from "Logging control part logging enable signal selection". ■(1) The logging enable's output mode is determined by "Logging control part logging enable mode setting". The Enable output processing output modes are shown below.
Page 275 ■Logging control part terminal list Module signal name Logic Description Connection Initial Pulse signal destination value clk100m  System clock cc2_top    usr_rst_n Reset for user circuit (the AND uc2_top between reset and internal operation start/stop) sim_ioe0_aival_vald_clk100m_reg A/D conversion value enable (E0) ai2_top 1shot@clk100m ...
Page 276 Module signal name Logic Description Connection Initial Pulse signal destination value cnt_iob1_32ring_2pha4multi_pha 32-bit ring counter (2-phase multiple Counter control  of 4) Phase A input (B1) part  cnt_iob1_32ring_2pha4multi_phb 32-bit ring counter (2-phase multiple Counter control of 4) Phase B input (B1) part ...
Page 277 Module signal name Logic Description Connection Initial Pulse signal destination value logctrl_uperr Logging control violation flag rising Output block  edge part  logctrl_downerr Logging control violation flag falling Output block edge part 11 FPGA INTERNAL CIRCUIT 11.4 User Circuit Block...
Page 278 Time division logging data generator The time division logging data generator performs the following operations. • Loads A/D conversion value (E0), A/D conversion value (E1), A/D conversion value (E2) Loads the following signals into the time division logging data generator. A/D conversion value (E0): sim_ioe0_aival_0_clk100m_reg to sim_ioe0_aival_b_clk100m_reg A/D conversion value (E1): sim_ioe1_aival_0_clk100m_reg to sim_ioe1_aival_b_clk100m_reg A/D conversion value (E2): sim_ioe2_aival_0_clk100m_reg to sim_ioe2_aival_b_clk100m_reg...
Page 279 1μs Logging control pulse pls_tmgpulse_log_clk100m_1shot_reg A/D conversion value enable (E0) sim_ioe0_aival_vald_clk100m_reg A/D conversion value enable (E1) sim_ioe1_aival_vald_clk100m_reg A/D conversion value enable (E2) sim_ioe2_aival_vald_clk100m_reg A/D conversion value 0...b (E0) DATA0_0 DATA0_1 DATA0_2 sim_ioe0_aival_0_clk100m_reg[15:0]...sim_ioe0_aival_b_clk100m_reg[15:0] A/D conversion value 0...b (E1) DATA1_0 DATA1_1 DATA1_2 sim_ioe1_aival_0_clk100m_reg[15:0]...sim_ioe1_aival_b_clk100m_reg[15:0] A/D conversion value 0...b (E2) DATA2_0...
Page 280 ■Loading A/D conversion value The A/D conversion value is loaded at "A/D conversion value enable". The data corresponding to loading is shown below. A/D conversion value enable A/D conversion value target signal Signal after loading A/D conversion Remarks (loaded if (1)) value sim_ioe0_aival_vald_clk100m_reg sim_ioe0_aival_0_clk100m_reg to...
Page 281 ■Logging data select signal generation, time division enable pulse generation, time division logging ON signal generation Generates "Logging data select (timd_logdat_sel_clk100m_reg)" and "Time division enable pulse (timd_divi_pulse_clk100m_1shot_reg)" that select the upper and lower A/D conversion values. The time division enable pulse is output twice at "Logging control pulse receive (pls_tmgpulse_log_clk100m_1shot_reg)"...
Page 282 ■Selector 1 Selects the logging data by "Logging data select (timd_logdat_sel_clk100m_reg)". (Assignment of [943:512] of [1023:0] in time division mode) Logging data select Bit assignment {48{0b}, timd_ioe2_aival_b_clk100m_reg[15:0], timd_ioe2_aival_a_clk100m_reg[15:0], timd_ioe2_aival_9_clk100m_reg[15:0], timd_ioe2_aival_8_clk100m_reg[15:0], timd_ioe2_aival_7_clk100m_reg[15:0], timd_ioe2_aival_6_clk100m_reg[15:0], timd_ioe2_aival_5_clk100m_reg[15:0], timd_ioe2_aival_4_clk100m_reg[15:0], timd_ioe2_aival_3_clk100m_reg[15:0], timd_ioe2_aival_2_clk100m_reg[15:0], timd_ioe2_aival_1_clk100m_reg[15:0], timd_ioe2_aival_0_clk100m_reg[15:0], timd_ioe1_aival_b_clk100m_reg[15:0], timd_ioe1_aival_a_clk100m_reg[15:0], timd_ioe1_aival_9_clk100m_reg[15:0], timd_ioe1_aival_8_clk100m_reg[15:0], timd_ioe1_aival_7_clk100m_reg[15:0], timd_ioe1_aival_6_clk100m_reg[15:0], timd_ioe1_aival_5_clk100m_reg[15:0], timd_ioe1_aival_4_clk100m_reg[15:0], timd_ioe1_aival_3_clk100m_reg[15:0], timd_ioe1_aival_2_clk100m_reg[15:0], timd_ioe1_aival_1_clk100m_reg[15:0],...
Page 283 Logging enable selector The logging enable selector outputs logging enable (logging start) to the logging block. It selects and outputs the logging enable signal from the digital input signal (B0 after filtering), digital input signal (B0 after digital control), and "Logging control part user logging control"...
Page 284 ■Logging enable selection According to the value set in "Logging control part logging enable signal selection (re_rs_usr_wreg_091_clk100m_reg[7: 0])", it selects the signal (logen_sel) to be output to the level immediately below. Logging enable signal selection is shown below. Logging control part logging logen_sel Description enable signal selection...
Page 285 ■Enable output processing The enable output processing part performs one-enable processing and automatic transfer mode processing. One-enable processing determines the output mode of "Logging enable (uc_logen_clk100m_reg)" according to the setting of "Logging control part logging enable mode setting". The operation and RTL diagram for each output mode are shown below. Logging control part Mode name Mode description...
Page 286 Also, if the logging enable output condition is not met, the logging control violation flag is output. The truth table of the logging control violation flag is shown below. Logging control part Always write register 14 Logging control One-enable Always read register 14 automatic transfer (re_rs_usr_alwreg_0e_cl trigger...
Page 287 Logging end trigger selector The logging end trigger selector outputs the logging end trigger to be output to the logging part. It selects "Digital input signal (B0 after filtering)" and "Digital output signal (B0 after digital control)" from "Logging control part end trigger signal selection", and selects "Logging end trigger"...
Page 288 In addition, the logging end trigger is selected and output by "User circuit logging mode selection (re_rs_usr_logmode_sel_1_0_clk100m_reg[0])". The truth table of the logging end trigger signal is shown below. User circuit logging mode selection Logging end trigger signal (uc_logend_clk100m_reg) (re_rs_usr_logmode_sel_1_0_clk100m_reg[0]) Detects and outputs the rising edge of logend_sel.
Page 289 User sampling pulse selector The user sampling pulse selector outputs the user sampling pulse to the logging block. It selects "Digital input signal (B0 after filtering)" and "Digital input signal (B0 after digital control)" from "Logging control part sampling pulse signal selection", and selects "User sampling pulse"...
Page 290 Output block part (uc3_msc_top) This module controls signal output to each block. The output signals are shown below. ■Block Diagram Other connection (uc3_msc_top) (1), re_rs_usr_wreg_000_clk100m_reg... Read data re_rs_usr_wreg_1ff_clk100m_reg uc_rs_usr_rreg_000_clk100m_reg[15:0]... uc_rs_usr_rreg_1ff_clk100m_reg[15:0] Test mode setting Read data output re_rs_usr_wreg_17f_clk100m_reg[0] A/D conversion value maximum/minimum hold (uc4_msc_maxmin) A/D conversion value 0 (E0) ai_ioe0_aival_0_clk100m_reg...
Page 291 ■Function List Function Description Read data output Outputs various statuses to check the internal status of the user circuit. Also, it selects and connects the FPGA internal status, "Write data (transient area)", and "Write data (cyclic area)" by setting "Test mode setting".
Page 292 Signal name Logic Description Connection Initial Pulse destination value signal pls_iob0_y_clk100m_reg[15:0]  Pulse output (B0) Pulse output 0000H  part   pls_iob0_y_dio485_clk100m_reg Pulse output (digital input/output) (B0) Pulse output part   pls_iob1_y_clk100m_reg[15:0] Pulse output (B1) Pulse output 0000H part ...
Page 293 Signal name Logic Description Connection Initial Pulse destination value signal di_ioe0_x_clk100m_reg[15:0]  Digital input signal (E0 after filtering) di2_top 0000H  (usr_rreg_188[15:0])   dio_ioe0_dio485_i_clk100m_reg Digital input signal (digital input/output E0 dio2_top after filtering) (usr_rreg_189[0])   di_ioe1_x_clk100m_reg[15:0] Digital input signal (E1 after filtering) di2_top 0000H (usr_rreg_18A[15:0])
Page 294 Signal name Logic Description Connection Initial Pulse destination value signal ai_ioe2_aival_0_clk100m_reg[15:0]  A/D conversion value CH0 ai2_top 0000H  (E2)(usr_rreg_1A7[15:0])   ai_ioe2_aival_1_clk100m_reg[15:0] A/D conversion value CH1 ai2_top 0000H (E2)(usr_rreg_1A8[15:0])   ai_ioe2_aival_2_clk100m_reg[15:0] A/D conversion value CH2 ai2_top 0000H (E2)(usr_rreg_1A9[15:0]) ...
Page 295 Signal name Logic Description Connection Initial Pulse destination value signal pls_iob1_plscnt_clk100m_reg[31:0]  Number of pulse outputs (B1) Pulse output 0000_0000H  (usr_rreg_1CD[15:0], usr_rreg_1CE[15:0]) part   pls_iob2_plscnt_clk100m_reg[31:0] Number of pulse outputs (B2) Pulse output 0000_0000H (usr_rreg_1CF[15:0], usr_rreg_1D0[15:0]) part   pls_ioe0_plscnt_clk100m_reg[31:0] Number of pulse outputs (E0) Pulse output...
Page 296 ■A/D conversion value maximum/minimum hold Holds the maximum and minimum values of A/D conversion values input from the extension module (E0, E1, E2). The maximum initial value is set to 8000H and the minimum initial value is set to 7FFFH, and when "A/D conversion value enable" is set to Enable (1), they are compared with the A/D conversion value and held.
Page 297 ■Digital output control Selects and outputs the digital output signal after digital control and output signal of the pulse output part. Also, HOLD/CLEAR is executed when "Microcomputer system error notification" is set to Enable (1), depending on the setting value of "Digital output HOLD/CLEAR".
Page 298 ■General-purpose output Outputs the general-purpose input (cpu_intpl_in) to the general-purpose output (cpu_intpl_out) in one flip-flop level (clk100m). Notes and restrictions for the sample circuit ■Safety circuit Provide a safety circuit that operates on the safe side according to the error cause of your system. In the sample circuit, the MCU system error notification (usr_micon_syserr) (FPGA register address: 1000_A004H) has an error (1) and implements a HOLD/CLEAR circuit that holds (holding the previous value) or clears (0 fixed output) the output.
Page 299: Part 6 Functions
PART 6 FUNCTIONS This part consists of the following chapter. 12 FUNCTIONS...
Page 300: Chapter 12 Functions
FUNCTIONS This chapter describes the details of the functions that can be used in the FPGA module and how to set them. 12.1 Function List The following table lists the functions of the FPGA module. Item Description Reference FPGA download function Writes the created configuration data to the configuration ROM inside the FPGA Page 300 FPGA Download Function module.
Page 301: Operation Mode Shift At Power-On
12.2 Operation Mode Shift at Power-On The FPGA module enters one of the following operation modes when the power is turned on. • CC-Link IE TSN communication mode • CC-Link IE TSN synchronous communication mode • Standalone mode • Standalone mode (IP address initialization) •...
Page 302: Fpga Download Function
12.3 FPGA Download Function Writes the created configuration data to the FPGA module. There are two writing methods, as follows. • How to write via JTAG ( Page 302 How to write via JTAG) • How to write via Ethernet ( Page 305 How to write via Ethernet) Configuration data Configuration data created in advance with FPGA design software is required to perform an FPGA download.
Page 303 Error information If writing is interrupted due to cable disconnection during FPGA download, check for messages on the windows of the FPGA design software and FPGA module configuration tool, and the communication environment, such as the cable connection status, and then perform the writing operation again. Precautions •...
Page 304: How To Write Via Jtag
How to write via JTAG In this method, the personal computer and the FPGA module are connected one-to-one with the FPGA download cable, and the configuration data is written to the FPGA module via JTAG. Use JIC format or SOF format files as configuration data. Application Software File format...
Page 305 Procedure for FPGA download The following describes the procedure to write configuration data via JTAG. Operating procedure Prepare configuration data. Prepare configuration data of .jic files or .sof files. For how to convert .sof files to .jic files, refer to the following. Page 309 Procedure for conversion from SOF format to JIC format and RPD format Connect an FPGA download cable.
Page 306 Select the checkbox as shown below and click the [Start] button. The download is complete. When the download has been completed, the FPGA module performs the FPGA configuration. ( Page 312 Configuration) Turn off the function setting switch 5 and restart the error detection for FPGA. When FPGA control automatic start setting is set to Disable, turn on FPGA control start request (RY0) to start FPGA control.
Page 307: How To Write Via Ethernet
How to write via Ethernet In this method configuration data from the FPGA module configuration tool is written to the configuration ROM via Ethernet. By connecting a personal computer to an available port on the same network as the FPGA module, downloading can be performed to any FPGA module connected to the same network.
Page 308 Procedure for FPGA download The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Prepare configuration data. Create RPD format files from SOF format files. For how to convert SOF format files to RPD format files, refer to the following. Page 309 Procedure for conversion from SOF format to JIC format and RPD format Connect to the network with an Ethernet cable.
Page 309 In "Environment setting", set "PC side setting" and "Monitor Timer setting". [Menu]  [Environment setting] Item Description PC side setting Adapter Select the adapter on the personal computer side that is connected to the FPGA module. IP address When an adapter is selected, the IP address of the target adapter is automatically input. If the adapter is "Not Specified", it will be blank.
Page 310 Select the folder in which the configuration data is saved. Click the [Download Execution] button. When the download has been completed successfully, the FPGA module performs the FPGA configuration. After FPGA configuration, it will enter one of the following states depending on the setting for "FPGA control automatic start setting".
Page 311: Procedure For Conversion From Sof Format To Jic Format And Rpd Format
Procedure for conversion from SOF format to JIC format and RPD format The following describes the procedure to convert the file format from SOF format to JIC format and RPD format. Operating procedure Start FPGA development software. Open the "Convert Programming File" window. [File] ...
Page 312 The device of the FPGA is input. Change the file name of JIC format file if necessary. Click the [Generate] button. A JIC format file and an RPD format file are generated in the 10_layout folder. 12 FUNCTIONS 12.3 FPGA Download Function...
Page 313: Fpga Configuration Function
12.4 FPGA Configuration Function The FPGA module performs FPGA configuration when:  Upon power-on or remote reset  At the time of FPGA download (configuration data file is JIC format, RPD format)  At the time of FPGA download (configuration data file is SOF format) For , configuration is performed using the configuration data saved in the configuration ROM inside the FPGA module.
Page 314 ■User circuit part parameter size The Writing data (transient area) of the FPGA register in the user circuit part can be saved in non-volatile memory as FPGA parameters from the start address to the size specified in the "User circuit part parameter size". After FPGA configuration is complete, parameters of a size equivalent to that saved in non-volatile memory are set to Writing data (transient area) (FPGA register address: 1000_B000H to 1000_B2FFH).
Page 315 The error is not cleared even after the error clear request flag (RYA) was turned off and on. Also, FPGA control will not start even if the FPGA control start request (RY0) is turned off and on. ■Precautions when saving parameters •...
Page 316 FPGA parameter ■FPGA register areas and remote buffer memory FPGA parameters can be saved in non-volatile memory inside the FPGA module. The saved FPGA parameters are transferred to the FPGA register areas and remote buffer memory when FPGA configuration is completed successfully. Classification FPGA function block FPGA parameter Item...
Page 317: Fpga Control Function
12.5 FPGA Control Function The FPGA standard circuit and user circuits can be started or stopped. Starting FPGA control FPGA control is started by turning off and on FPGA control start request (RY0). The starting order of the FPGA is shown below.
Page 318 ADC and DAC conversions do not start at the same time as the standard circuit and user circuit. Setting completion for ADC and DAC can be determined by checking b0 of Always write register 15 (usr_alwreg_0F) (FPGA register address: 1000_A02EH) of the user circuit part. Stopping FPGA control FPGA control is stopped by turning off and on FPGA control stop request (RY1).
Page 319 FPGA control automatic start When "FPGA control automatic start setting" is "Enable", FPGA control starts automatically after configuration is complete. The "FPGA control automatic start delay setting" can be used to set a delay (seconds) before automatic start. When a moderate error is cleared by turning on and off the error clear request flag (RYA), if "FPGA control automatic start setting"...
Page 320 Continue FPGA control In CC-Link IE TSN communication mode, the "FPGA control continuation setting" allows selecting whether to continue or stop FPGA control according to the CPU module status and data link status. Depending on setting for the "FPGA control continuation setting", the FPGA operates as follows.
Page 321 When "FPGA control continuation setting" is set to "Continue" Continues FPGA control regardless of the data link status. Cyclic transmission Cyclic transmission Disconnected Data link status Disconnected being performed being performed FPGA logic control state Control being executed Stopping FPGA controlling flag (RX0) FPGA control stop request (RY1)
Page 322 Output HOLD/CLEAR setting Sets whether to retain (HOLD) or clear (CLEAR) the value that was output immediately before FPGA control stops. When FPGA control is stopped, the external output will be in the following states depending on the HOLD/CLEAR setting. Output type FPGA parameter HOLD/CLEAR...
Page 323: Fpga Register Access Function
12.6 FPGA Register Access Function Reads from and writes to the FPGA register areas from the master station program. There are two methods for reading from and writing to FPGA register areas. The appropriate method should be selected. • Remote register method •...
Page 324 Details Reading data (cyclic area) (usr_rreg_180 to usr_rreg_1FF) (FPGA register address: 1000_BB00H to 1000_BBFEH) are read to the FPGA register read area (RWr10 to RWr8F). Also, the FPGA register write area (RWw10 to RWw8F) is Writing data (cyclic area) (usr_wreg_180 to usr_wreg_1FF) (FPGA register address: 1000_B300H to 1000_B3FEH). When designing the user circuit, reading data (cyclic area) (usr_rreg_180 to usr_rreg_1FF) (FPGA register address: 1000_BB00H to 1000_BBFEH) and writing data (cyclic area) (usr_wreg_180 to usr_wreg_1FF) (FPGA register address: 1000_B300H to 1000_B3FEH) can be accessed cyclically from the program.
Page 325 Allocation of read/write areas for FPGA register areas The values in the FPGA register write area (RWw10 to RWw8F) are written to the writing data (cyclic area) (usr_wreg_180 to usr_wreg_1ff) (FPGA register addresses: 1000_B300H to 1000_B3FEH). Also, reading data (cyclic area) (usr_rreg_180 to usr_rreg_1ff) (FPGA register addresses: 1000_BB00H to 1000_BBFEH) is read out to the FPGA register read area (RWr10 to RWr8F).
Page 326: Method Using Remote Buffer Memory
Method using remote buffer memory Any FPGA register can be read from and written to. It is used to write and read at specific timings such as the initial setting of FPGA register areas from the program. Data is updated between the remote buffer memory and the FPGA register areas when writing to the remote buffer memory or writing a read request.
Page 327 Details ■Write When a Write request (remote buffer memory address: 1203H) is requested (1), writing data 0 (remote buffer memory address: 1204H) to writing data 383 (remote buffer memory address: 1383H) are written, according to the number of words set for the write size (remote buffer memory address: 1202H), starting with the FPGA register that was set as the write start address (remote buffer memory address: 1200H, 1201H).
Page 328 ■Read When a Read request (remote buffer memory address: 1403H) is requested (1), the number of words (read size) set in (remote buffer memory address: 1402H) is read to reading data 0 (remote buffer memory address: 1404H) to reading data 383 (remote buffer memory address: 1583H), from the FPGA register areas set for the read start address (remote buffer memory address: 1400H, 1401H).
Page 329: Logging Function
12.7 Logging Function The logging part of the FPGA acquires the external input/output from the user circuit, count values, and other sources at the timing of when the sampling pulse is input, and writes them to DDR3L SDRAM. Since data before and after the occurrence of a problem can be stored, it can be used for phenomenon analysis.
Page 330: Logging Control
Logging control The remote I/O signals that control the logging operation are shown below. • Logging start flag (RX3) • FTP transfer completion flag (RX4) • FTP transfer error completion flag (RX5) • FPGA control stop while data collection flag (RX6) •...
Page 331 Logging operation status and availability of various requests ■Control by remote output signal Control by the remote output signal may or may not be executed depending on the logging operation status. The following shows whether the logging operation state can be executed or not. Remote output signals Logging operation state monitor (RWrB) Description...
Page 332 Retransmission and transfer of logging data If the below described  to  occurs, the transfer of logging data to the FTP server will be incomplete. In this state, whether to resend or transfer logging data to the FTP server can be selected. •...
Page 333: Record Details
Record details A 512-bit record, which is a combination of 432-bit logging data and 80-bit time data, is called a record. Records cannot be resized. DDR3L SDRAM Record 0 User circuit logging data 0...431 Record 1 Record 2 432bit Record 3 512bit Logging data...
Page 334: Time Setting
Time setting Set the time of the timestamp added to the logging data. The FPGA module does not correct time information for daylight saving time. Set the time corrected for summer time in the FPGA module. CC-Link IE TSN communication mode Set the first time information distributed from the master station during data link with the master station.
Page 335: Operation Example
Operation example Here is an example of logging operation. Storage operation mode (linear buffer) In this mode, sampling is performed only for the logging data size after logging has started. This is used when the logging period is clear before logging starts. Logging start DDR3L SDRAM Record 0...
Page 336 Storage operation mode (ring buffer) In this mode, sampling is performed until logging is stopped at an arbitrary timing after logging is started. This is used when the logging period is not clear before logging starts. Logging start DDR3L SDRAM Record N + 1 Logging stop Record N + 2...
Page 337 Trigger operation mode (ring buffer) In this mode logging stops when a trigger occurs after logging has started. It is used to check the circuit status before and after the trigger occurs. After a trigger is generated, logging stops after sampling for the "Set number of sampling after trigger". Logging start DDR3L SDRAM Record 0...
Page 338 Operation examples for when the following parameters are set are shown. • "Logging function enable/disable": "Enable" • "Logging operation mode setting": "Trigger operation mode" • "Select logging start control": "Register setting value (RY3)" • "Select sampling pulses": "Logging cycle timing" •...
Page 339: Setting Method
Setting method Use the FPGA Module Configuration Tool to set parameters. ( Page 98 FPGA parameters) Operating procedure Set whether to enable or disable the logging function in "Logging function enable/disable". If set to "Disable", all parameters of the logging function will be disabled. Set the logging operation mode in "Logging operation mode setting".
Page 340: Logging Monitor
Logging monitor The remote register areas that can check the operating status of logging are shown below. • Logging operation state monitor (RWrB) ( Page 486 Logging operation status monitor) • Sampling count monitor (RWrC, RWrD) ( Page 487 Sampling count monitor) •...
Page 341: Precautions
Precautions Time information is not saved in the FPGA module. The time information is initialized when the module power of the FPGA module is turned off and on. When using time information in standalone mode, set the time from the SLMP-compatible device after the FPGA module has started.
Page 342: Ftp Client Function
12.8 FTP Client Function Transfers logging data collected in DDR3L SDRAM to the FTP server. Setting method Use the FPGA Module Configuration Tool to set parameters. ( Page 98 FPGA parameters) ■Setting the transfer destination FTP server Operating procedure Set the IP address of the destination FTP server in "FTP server IP address". Set the FTP server IP address to the same IP address class as the FPGA module.
Page 343 ■Logging data file name setting The basic file name of the logging data file name is a sequential 8-digit hexadecimal number. The number is the number of times the logging data was sent after the power of the FPGA module was turned on. In addition to the basic file name, the date, time and character string can be appended.
Page 344: File Saving Format Of Logging Data
File saving format of logging data When transferring logging data to an FTP server, the data can be converted to a CSV file before transfer. Setting method Use the FPGA Module Configuration Tool to set parameters. ( Page 95 Module parameters) Operating procedure Set "Logging data file storage type"...
Page 345 Binary format Binary format is comprised of header information and record data. For details on the record data when the file is saved in binary format, refer to the following. Page 331 Record details Header information Fixed to 0 (16 bits) (256 bits) Time division mode (16 bits)*¹...
Page 346 CSV format The format of logging data saved in a CSV file is shown below. Row name Column Column name Description index File information 1st row File type Fixed characters are stored. [LOGGING] 2nd row Model information_file version Fixed characters are stored. NZ2GN2S-D41_1 3rd row No.
Page 347 ■Data type output character The correspondence between the data type specified in CSV Format setting and the data type output characters in the CSV file is shown below. Data type Output type Output Content Binary format BIT[1;0] Word [Signed] Decimal format SHORT[DEC.0] Word [unsigned] Decimal format...
Page 348: Operation Example
Operation example An operation example of the FTP client function is shown. Logging data transfer When "Select logging start control" is "Register setting value (RY3)", the control for transferring logging data after sampling is completed of 256 points is shown below. Logging start flag (RX3) Logging start request...
Page 349 Resend logging data The following shows how to transfer logging data again when logging data transfer is stopped due to FTP communication error or other cause when "Select logging start control" is "Register setting value (RY3)". Logging start flag (RX3) Ú...
Page 350 Logging data transfer using sample circuit The following shows the control for transferring logging data after sampling completion of 256 points when "Select logging start control" is "User circuit output". FTP transfer completion flag (RX4) FTP transfer error completion flag (RX5) FTP transfer count monitor (RWrE) Collection start Collecting...
Page 351 Logging data retransmission using sample circuit The figure below shows the control for transferring logging data again in the following situation: When "Select logging start control" is "User circuit output", the transfer of logging data is stopped due to a communication error after sampling 256 points. Logging start flag (RX3) Logging start request (RY3) Ò...
Page 352: Precautions
Precautions Set the interval from the start of logging data file transfer to the start of the next transfer to 3 seconds or more. An FTP communication error may occur if logging data files are transferred at intervals of less than 3 seconds. If an FTP communication error occurs, FTP open abnormality (error code: 1401) is stored to Latest error code (RWr0) and Error status flag (RXA) turns on.
Page 353: Slmp Communication Function
12.9 SLMP Communication Function SLMP can be used to communicate with the FPGA module. For details on SLMP, refer to the following.  SLMP Reference Manual Applicable commands SLMP commands Description Type Operation Command Subcommand Remote Control Remote Reset 1006H 0000H Execute a remote RESET to the FPGA module.
Page 354 Communications settings When communicating with the FPGA module via SLMP, use the following. • TCP/UDP: UDP • Port: 45239 • Code: binary code Usage method Use the SLMPSND instruction to send SLMP commands to the FPGA module from the CPU module. For details on the SLMPSND command, refer to the following.
Page 355: Cc-Link Ie Tsn Network Synchronous Communication Function
12.10 CC-Link IE TSN Network Synchronous Communication Function Reads and writes to the FPGA at the synchronous cycle of a master station that supports the CC-Link IE TSN network synchronous communication function. This enables an A/D converter module to operate at the same timing as other remote stations on the same network. Applicable version When using the CC-Link IE TSN network synchronous communication function, check the version of the master station.
Page 356 Setting method Calculate synchronization cycles from the formula below. Synchronization cycle = Basic period (Communication period interval setting)  Magnification Item Description Basic period (Communication period interval setting) Setting values of the communication period interval setting of master station parameters Magnification Magnification that is determined by the following master station parameters •...
Page 357 Operating procedure Display the "CC-Link IE TSN Configuration" window. [Navigation Window]  [Parameter]  [Module Information]  Model  [Basic Setting]  [Network Configuration Settings] Set "Network Synchronous Communication" to "Synchronous". • To use the CC-Link IE TSN network synchronous communication function for the FPGA module, enable the CC-Link IE TSN network synchronous communication function of the master station.
Page 358 Timing chart ■Read The FPGA status is read at the timing of the synchronization cycle and sent to the master station at the next synchronization cycle. Synchronization cycle of master station Read processing External input signal Input status of (1) Input status of (2) Input status of (3) (RX10 to RX6F)
Page 359 ■Write The value to be written to the FPGA register is received at the timing of the synchronization cycle, and written to the FPGA at the timing of the next synchronization cycle. Synchronization cycle of master station Write processing External output signal Output value Output value of (1) Output value of (2)
Page 360 ■Synchronization signal to FPGA At the timing of the synchronization cycle, Always write register 13 (usr_alwreg_0D) (FPGA register address: 1000_A02AH) is stored with sync signal (1). Always write register 13 (usr_alwreg_0D) (FPGA register address: 1000_A02AH) allows for creation of a user circuit that operates at the synchronization cycle timing. Synchronization cycle of master station Write processing...
Page 361 ■Starting FPGA control The start of FPGA control by turning on FPGA control start request (RY0) is accomplished after the external output signals (RY10 to RY6F) have been stored to Output value setting (B0) (oport_iob0y_odata) (FPGA register address: 1000_4010H) to Output value setting (E2) (oport_ioe2y_odata) (FPGA register address: 1000_401CH).
Page 362: Module Power Supply Voltage Drop Detection Function
12.11 Module Power Supply Voltage Drop Detection Function This function detects a voltage drop of the module power supply. This function makes troubleshooting easy when the voltage of power supplied to the FPGA module drops or when poor connection in the wiring occurs. Note that the voltage to be monitored for a module power supply voltage drop is 20.4V. Operation If a drop in the voltage of the module power supply is detected, the module enters the following state and an error is notified.
Page 363: Firmware Update Function
Firmware update file When the firmware update file is necessary, please consult your local Mitsubishi representative. The file name of firmware update file is listed below. Model name File name NZ2GN2S-D41D01 CCIET_FPGA.SYF NZ2GN2S-D41P01 NZ2GN2S-D41PD02 12 FUNCTIONS 12.12 Firmware Update Function...
Page 364 Firmware Update Tool are the same (it does not matter if the model names of the actual modules are different). For example, set NZ2GN2S-D41P01 as the model name of all FPGA modules for which the firmware is to be updated.
Page 365 ■"Application Settings" window Window Displayed items Set the following items in the "Application Settings" window. Classification Item Setting range Description PC Settings IP Address 0.0.0.1 to 223.255.255.254 Set the IP address of the personal computer. Port Number 0, 49152 to 65535 Set 0.
Page 366 Error information list The following table lists the error information of FPGA module-specific errors that can occur when a firmware update is performed. Error Error name Description and cause Action information 0001H File error A file that cannot be used for the FPGA Review the firmware update file specified with the CC-Link IE TSN module to be updated is specified.
Page 367: Part 7 Sample Circuit
PART 7 SAMPLE CIRCUIT This part consists of the following chapters. 13 SAMPLE CIRCUIT IN STANDALONE MODE 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE...
Page 368: Chapter 13 Sample Circuit In Standalone Mode
This section describes the function to invert the digital signal input to X0 (B0) and output it to Y0 (B0). System configuration Output inversion FPGA Module X0(B0) Configuration Tool Y0(B0) Digital signal input X0 (B0) Sensor Digital signal output Y0 (B0) FPGA module FPGA module: NZ2GN2S-D41P01 13 SAMPLE CIRCUIT IN STANDALONE MODE 13.1 When Using the Inversion Output Function...
Page 369 The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Create the project with the following settings. Set NZ2GN2S-D41P01 as the connected main module. [Project]  [New] Click the [OK] button. Enter the IP address of the FPGA module to be connected in the "Connection destination setting" window.
Page 370 From the "Module Parameter" window, set the values of the module parameters. [Menu]  [Module Parameter] From the "FPGA parameter" window, set the values of the FPGA parameters. [Menu]  [FPGA parameter] 13 SAMPLE CIRCUIT IN STANDALONE MODE 13.1 When Using the Inversion Output Function...
Page 371 Set the values of the user circuit part parameters in the "User circuit part parameter setting" window. [Menu]  [FPGA parameter]  [User circuit part parameter setting]  <Detailed settings> Write the set parameters. [Online]  [Parameter write (Memory + Non-volatile memory)] Click the [Yes] button.
Page 372 Implementation method and check method Check that the digital signal input to X0 (B0) is inverted and the inverted signal is output. Follow the steps below to monitor the FPGA register using the FPGA Module Configuration Tool. Operating procedure After writing the parameters, turn the power off and on to restart the module. Input a digital signal from the sensor to X0 (B0).
Page 373: When Using The Pulse Count Function
FPGA Module Configuration Tool Pulse input Phase A Phase B Encoder FPGA module FPGA module: NZ2GN2S-D41P01 Module parameter The setting value of the module parameter is shown below. Setting item Setting value FPGA control automatic start setting Enable FPGA parameter The setting values of the FPGA parameters to be set are shown below.
Page 374 The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Create the project with the following settings. Set NZ2GN2S-D41P01 as the connected main module. [Project]  [New] Click the [OK] button. Enter the IP address of the FPGA module to be connected in the "Connection destination setting" window.
Page 375 From the "Module Parameter" window, set the values of the module parameters. [Menu]  [Module Parameter] From the "FPGA parameter" window, set the values of the FPGA parameters. [Menu]  [FPGA parameter] 13 SAMPLE CIRCUIT IN STANDALONE MODE 13.2 When Using the Pulse Count Function...
Page 376 Set the values of the user circuit part parameters in the "User circuit part parameter setting" window. [Menu]  [FPGA parameter]  [User circuit part parameter setting]  <Detailed settings> Write the set parameters. [Online]  [Parameter write (Memory + Non-volatile memory)] Click the [Yes] button.
Page 377 Implementation method and check method Operating procedure After writing the parameters, turn the power off and on to restart the module. Input pulses from the encoder. In "Device/Register batch monitor", monitor the following FPGA register areas and check that the counter value is increased.
Page 378: When Using The D/A Conversion Function
This section describes the function to D/A-convert a digital value and output a voltage in CH0 (E0). System configuration example FPGA Module Configuration Tool FPGA module Voltage output (-9.9 to 9.9V) FPGA module: NZ2GN2S-D41P01+NZ2EX2S-D41A01 Module parameter The setting value of the module parameter is shown below. Setting item Setting value FPGA control automatic start setting Enable FPGA parameter The setting values of the FPGA parameters to be used are shown below.
Page 379 The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Create the project with the following settings. Set NZ2GN2S-D41P01 as the connected main module and NZ2EX2S-D41A01 as the connection extension module. [Project]  [New] Click the [OK] button.
Page 380 From the "Module Parameter" window, set the values of the module parameters. [Menu]  [Module Parameter] From the "FPGA parameter" window, set the values of the FPGA parameters. [Menu]  [FPGA parameter] 13 SAMPLE CIRCUIT IN STANDALONE MODE 13.3 When Using the D/A Conversion Function...
Page 381 Set the values of the user circuit part parameters in the "User circuit part parameter setting" window. [Menu]  [FPGA parameter]  [User circuit part parameter setting]  <Detailed settings> Write the set parameters. [Online]  [Parameter write (Memory + Non-volatile memory)] Click the [Yes] button.
Page 382: When Using The Pulse Output Function
ON width 100μs 100μs 100μs FPGA module Reference pulse Total of 100 pulses FPGA module: NZ2GN2S-D41P01 Module parameter The setting value of the module parameter is shown below. Setting item Setting value FPGA control automatic start setting Enable FPGA parameter The setting values of the FPGA parameters to be set are shown below.
Page 383 The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Create the project with the following settings. Set NZ2GN2S-D41P01 as the connected main module. [Project]  [New] Click the [OK] button. Enter the IP address of the FPGA module to be connected in the "Connection destination setting" window.
Page 384 From the "Module Parameter" window, set the values of the module parameters. [Menu]  [Module Parameter] From the "FPGA parameter" window, set the values of the FPGA parameters. [Menu]  [FPGA parameter] 13 SAMPLE CIRCUIT IN STANDALONE MODE 13.4 When Using the Pulse Output Function...
Page 385 Set the values of the user circuit part parameters in the "User circuit part parameter setting" window. [Menu]  [FPGA parameter]  [User circuit part parameter setting]  <Detailed settings> Write the set parameters. [Online]  [Parameter write (Memory + Non-volatile memory)] Click the [Yes] button.
Page 386: When Using The Logging Function
Logging start/stop switch FPGA module FPGA module: NZ2GN2S-D41P01 Operation In this connection example, the input of X6 (B0) controls the start and stop of logging, and the pulse input of X4 (B0) controls the sampling timing. This enables the logging of the 32-bit ring counters that count pulses input to X1 (B0) and X2 (B0) with the pulse width of 100s for 2-phase multiple of 4.
Page 387 Module parameter The setting values of the module parameters are shown below. Setting item Setting value Logging function enable/disable Enable Logging data file storage type CSV Files CSV Format setting 0 (bit0~bit15) Bit, binary format CSV Format setting 6 (bit96~bit111) Bit, binary format CSV Format setting 7 (bit112~bit127) Double Word [Unsigned], decimal format...
Page 388 Logging data The data to be logged is shown below. First First Logging data word Description Digital input signal (after filtering) (B0) Digital input signal (after filtering) (B1) Digital input signal (after filtering) (B2) Digital input signal (after filtering) (E0) Digital input signal (after filtering) (E1) Digital input signal (after filtering) (E2) Counter control part...
Page 389 The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Create the project with the following settings. Set NZ2GN2S-D41P01 as the connected main module. [Project]  [New] Click the [OK] button. Enter the IP address of the FPGA module to be connected in the "Connection destination setting" window.
Page 390 Set the value of the CSV format setting in the "Logging data storage format setting" window. [Menu]  [Module Parameter]  [Logging setting]  [CSV Format setting]  <Detailed settings> Click the [OK] button. From the "FPGA parameter" window, set the values of the FPGA parameters. [Menu] ...
Page 391 Set the values of the user circuit part parameters in the "User circuit part parameter setting" window. [Menu]  [FPGA parameter]  [User circuit part parameter setting]  <Detailed settings> Write the set parameters. [Online]  [Parameter write (Memory + Non-volatile memory)] Click the [Yes] button.
Page 392: Logging A/D Conversion Values
FPGA module Sensor FPGA module: NZ2GN2S-D41P01+NZ2EX2S-D41A01 Operation The force of X6 (B0) controls the start and stop of logging, and logs the A/D conversion values of the sensor connected to CH0 (E0). Logging is performed for each A/D conversion timing of E0.
Page 393 Module parameter The setting values of the module parameters are shown below. Setting item Setting value Logging function enable/disable Enable Logging data file storage type Binary file FTP server IP address IP address of the FTP server to be used Login name Login name of the FTP server to be used Password...
Page 394 Logging data The data to be logged is shown below. First First Logging data word Description Digital input signal (after filtering) (B0) Digital input signal (after filtering) (B1) Digital input signal (after filtering) (B2) Digital input signal (after filtering) (E0) Digital input signal (after filtering) (E1) Digital input signal (after filtering) (E2) Counter control part 32-bit ring counter...
Page 395 The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Create the project with the following settings. Set NZ2GN2S-D41P01 as the connected main module and NZ2EX2S-D41A01 as the connection extension module. [Project]  [New] Click the [OK] button.
Page 396 From the "FPGA parameter" window, set the values of the FPGA parameters. [Menu]  [FPGA parameter] Set the values of the user circuit part parameters in the "User circuit part parameter setting" window. [Menu]  [FPGA parameter]  [User circuit part parameter setting]  <Detailed settings> Write the set parameters.
Page 397 Click the [Yes] button. Implementation method and check method Operating procedure After writing the parameters, turn the power off and on to restart the module. Start logging. After 256 records of data have been collected, FTP transfer will start. Check the file transferred over FTP. If FPGA control stops during logging of A/D conversion values in time division mode, logging will not be performed normally.
Page 398: Chapter 14 Sample Circuit In Cc-Link Ie Tsn Communication Mode
Total 100 pulse output • CPU module: R120CPU • Master module: RJ71GN11-T2 (X0 to X1F/Y0 to Y1F) • Input module: RX10 (X20 to X2F) • Main module: NZ2GN2S-D41P01 • Extension module: NZ2EX2S-D41A01 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE...
Page 399 Assignment of link devices Master station (station number 0) Remote station (station number 1) FPGA register CPU module Master module FPGA module Remote input RX Device X Remote input RX X1000 · · · RX6F RX6F X106F Device Y Remote output RY Remote output RY Y1000 ·...
Page 400 Setting of the master station Connect the engineering tool to the CPU module of the master station and set parameters. Operating procedure Set the CPU module as follows. [Project]  [New] In "CPU Parameter", set "Extended Mode (iQ-R Series Mode)" for "Link Direct Device Setting". [CPU Parameter] ...
Page 401 Set the "Required Settings" as follows. [Navigation Window]  [Parameter]  [Module Information]  [RJ71GN11-T2]  [Required Settings] Set the items in "Basic Settings" as follows. [Navigation Window]  [Parameter]  [Module Information]  [RJ71GN11-T2]  [Basic Settings] 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE...
Page 402 Set the network configuration as follows. [Navigation Window]  [Parameter]  [Module Information]  [RJ71GN11-T2]  [Basic Settings]  [Network Configuration Settings]  <Detailed Setting> Click the [Close with Reflecting the Setting] button to close the "CC-Link IE TSN Configuration" window. Set the refresh settings as follows.
Page 403: Precautions For Programming
14.1 Precautions for Programming This section describes the precautions when creating programs for setting the CC-Link IE TSN communication mode. Program for cyclic transmission For a program for cyclic transmission, provide interlock between the following link special relay (SB) and the link special register (SW).
Page 404: When Using The Inversion Output Function
The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Create the project with the following settings. Set NZ2GN2S-D41P01 as the connected main module and NZ2EX2S-D41A01 as the connection extension module. [Project]  [New] Click the [OK] button.
Page 405 From the "FPGA parameter" window, set the values of the FPGA parameters. [Menu]  [FPGA parameter] Set the values of the user circuit part parameters in the "User circuit part parameter setting" window. [Menu]  [FPGA parameter]  [User circuit part parameter setting]  <Detailed settings> Write the set parameters.
Page 406 Click the [Yes] button. Click the [Yes] button. 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE 14.2 When Using the Inversion Output Function...
Page 407: When Using The Pulse Count Function
The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Create the project with the following settings. Set NZ2GN2S-D41P01 as the connected main module and NZ2EX2S-D41A01 as the connection extension module. [Project]  [New] Click the [OK] button.
Page 408 From the "FPGA parameter" window, set the values of the FPGA parameters. [Menu]  [FPGA parameter] Set the values of the user circuit part parameters in the "User circuit part parameter setting" window. [Menu]  [FPGA parameter]  [User circuit part parameter setting]  <Detailed settings> 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE 14.3 When Using the Pulse Count Function...
Page 409 Write the set parameters. [Online]  [Parameter write (Memory + Non-volatile memory)] Click the [Yes] button. Click the [Yes] button. 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE 14.3 When Using the Pulse Count Function...
Page 410: When Using The A/D Conversion Function
The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Create the project with the following settings. Set NZ2GN2S-D41P01 as the connected main module and NZ2EX2S-D41A01 as the connection extension module. [Project]  [New] Click the [OK] button.
Page 411 From the "FPGA parameter" window, set the values of the FPGA parameters. [Menu]  [FPGA parameter] Set the values of the user circuit part parameters in the "User circuit part parameter setting" window. [Menu]  [FPGA parameter]  [User circuit part parameter setting]  <Detailed settings> 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE 14.4 When Using the A/D Conversion Function...
Page 412 Write the set parameters. [Online]  [Parameter write (Memory + Non-volatile memory)] Click the [Yes] button. Click the [Yes] button. 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE 14.4 When Using the A/D Conversion Function...
Page 413: When Using The D/A Conversion Function
The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Create the project with the following settings. Set NZ2GN2S-D41P01 as the connected main module and NZ2EX2S-D41A01 as the connection extension module. [Project]  [New] Click the [OK] button.
Page 414 From the "FPGA parameter" window, set the values of the FPGA parameters. [Menu]  [FPGA parameter] Set the values of the user circuit part parameters in the "User circuit part parameter setting" window. [Menu]  [FPGA parameter]  [User circuit part parameter setting]  <Detailed settings> Write the set parameters.
Page 415 Click the [Yes] button. Click the [Yes] button. 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE 14.5 When Using the D/A Conversion Function...
Page 416: 14.6 When Using The Pulse Output Function
14.6 When Using the Pulse Output Function This section describes the function to generate 100 pulses with the pulse width of 100s and output them to External output signal Y1 (B0). Note that the digital signal is shown for 1-phase multiple of 1. FPGA parameter The setting values of the FPGA parameters to be set are shown below.
Page 417 The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Create the project with the following settings. Set NZ2GN2S-D41P01 as the connected main module and NZ2EX2S-D41A01 as the connection extension module. [Project]  [New] Click the [OK] button.
Page 418 Set the values of the user circuit part parameters in the "User circuit part parameter setting" window. [Menu]  [FPGA parameter]  [User circuit part parameter setting]  <Detailed settings> Write the set parameters. [Online]  [Parameter write (Memory + Non-volatile memory)] Click the [Yes] button.
Page 419: When Using The Logging Function
14.7 When Using the Logging Function This section describes how to log the value of 32-bit ring counters used in the usage example of the counter control part. In addition to the parameters set as described in the section below, set the parameters as described on this page. Page 405 When Using the Pulse Count Function Module parameter The setting values of the module parameters are shown below.
Page 420 The procedure using the FPGA Module Configuration Tool is shown below. Operating procedure Create the project with the following settings. Set NZ2GN2S-D41P01 as the connected main module and NZ2EX2S-D41A01 as the connection extension module. [Project]  [New] Click the [OK] button.
Page 421 Set the value of the CSV format setting in the "CSV Format setting" window. [Menu]  [Module Parameter]  [Logging setting]  [CSV Format setting]  <Detailed settings> Click the [OK] button. From the "FPGA parameter" window, set the values of the FPGA parameters. [Menu] ...
Page 422 Click the [Yes] button. 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE 14.7 When Using the Logging Function...
Page 423: Program Examples
14.8 Program Examples This section describes program examples for using the functions of the sample circuit. Devices to be used ■Common device Device Description SB0049 Data link status of the own station (master station) SW00B0.0 Data link status of each station (station number 1) Nesting (station number 1) Communication ready flag (station number 1) X100A...
Page 424 ■Devices to be used for the pulse output function Device Description Pulse output enable command Output pulse count (B0) (lower side) Output pulse count (B0) (upper side) W105B Pulse output part output pulse count (lower side) (B0) W105C Pulse output part output pulse count (upper side) (B0) W1148 Pulse output part pulse output enable (B0) ■Devices to be used by the logging function...
Page 425 Program example 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE 14.8 Program Examples...
Page 426 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE 14.8 Program Examples...
Page 427 (7) Start FPGA control. Start FPGA control when FPGA control start/stop command (X20) is ON. Stop FPGA control when FPGA control start/stop command (X20) is OFF. (17)Monitor the count value when the pulse count function is used. (21)Set the preset data when the pulse count function is used. (27)Preset the counter value when the pulse count function is used.
Page 428 MEMO 14 SAMPLE CIRCUIT IN CC-LINK IE TSN COMMUNICATION MODE 14.8 Program Examples...
Page 429 PART 8 TROUBLESHOOTING This part consists of the following chapters. 15 MAINTENANCE AND INSPECTION 16 CC-Link IE TSN/CC-Link IE Field DIAGNOSTICS 17 MODULE DIAGNOSTICS WITH THE FPGA MODULE CONFIGURATION TOOL 18 CHECKING THE LEDS 19 UNIT TEST 20 TROUBLESHOOTING BY SYMPTOM 21 TROUBLESHOOTING DURING FPGA DEVELOPMENT 22 TROUBLE EXAMPLES of DC INPUT/OUTPUT 23 CHECK/CLEAR ERROR CODES...
Page 430: Chapter 15 Maintenance And Inspection
MAINTENANCE AND INSPECTION There is no special item to be inspected for the FPGA module. However, to maintain the best condition of the system, perform the inspection in accordance with the items described in the following manual.  MELSEC iQ-R Module Configuration Manual 15 MAINTENANCE AND INSPECTION...
Page 431 MEMO 15 MAINTENANCE AND INSPECTION...
Page 432: Chapter 16 Cc-Link Ie Tsn/Cc-Link Ie Field Diagnostics
CC-Link IE TSN/CC-Link IE Field DIAGNOSTICS For CC-Link IE TSN, monitor the status and conduct an operation test. For details on CC-Link IE TSN/CC-Link IE Field diagnostics, refer to the following.  User's manual for the master station used Remote reset Perform the following operation to remotely reset a selected FPGA module.
Page 433 Checking station information The information of the FPGA module in data linking is displayed on the "Station Information List" window. Information on the FPGA module, such as the production information, firmware version, and module-specific information, can be checked by clicking the [Station Information List] button in the "CC-Link IE TSN/CC-Link IE Field Diagnostics" window. The FPGA module displays the current status of function setting switches or the status of the switches when the power is turned on, as module-specific information.
Page 434: Chapter 17 Module Diagnostics With The Fpga Module Configuration Tool
MODULE DIAGNOSTICS WITH THE FPGA MODULE CONFIGURATION TOOL The FPGA Module Configuration Tool displays the basic information of the FPGA module and monitors the status. For details on module diagnostics using the FPGA Module Configuration Tool, refer to the following. Page 121 Module diagnostics 17 MODULE DIAGNOSTICS WITH THE FPGA MODULE CONFIGURATION TOOL...
Page 435 MEMO 17 MODULE DIAGNOSTICS WITH THE FPGA MODULE CONFIGURATION TOOL...
Page 436: Chapter 18 Checking The Leds
CHECKING THE LEDS This section describes how to troubleshoot the system by the LEDs. When the PW LED does not turn on When the PW LED does not turn on, check the following items. Check item Action Is any LED other than the PW LED turned on? When any LED other than the PW LED turns on, the possible cause is a hardware error.
Page 437 When the P1 LINK LED or P2 LINK LED turns off When the P1 LINK LED or P2 LINK LED turns off, check the following items. Check item Action Are Ethernet cables used compliant with the Replace the cable with an Ethernet cable compliant with the relevant standard. ...
Page 438 When the DATA LINK LED flashes When the DATA LINK LED flashes in CC-Link IE TSN communication mode, check the following items. Check item Action Do the IP addresses match? Match the IP address of the FPGA module with the IP address that is set in the network configuration settings of the master station.
Page 439 Check item Action Has any error occurred in the FPGA module? If an error has occurred in the FPGA module, a network parameter may be set to a value that the FPGA module cannot handle. If following errors have occurred, eliminate them in order from the top one. ( Page 443 TROUBLESHOOTING DURING FPGA DEVELOPMENT) •...
Page 440: Chapter 19 Unit Test
UNIT TEST Run a unit test to check if there is any abnormality in the hardware of the FPGA module. Operating procedure Download the configuration data in which the sample circuit is configured to the FPGA module. Power off the FPGA module. Connect P1 and P2 of the FPGA module with an Ethernet cable.
Page 441 MEMO 19 UNIT TEST...
Page 442: Chapter 20 Troubleshooting By Symptom
TROUBLESHOOTING BY SYMPTOM Troubleshooting by symptom is suitable for the case where the FPGA module fails to operate normally even though no error has occurred in the FPGA module. If an error occurs in the FPGA module, identify the cause of the error using the engineering tool.
Page 443 When CC-Link IE TSN/CC-Link IE Field diagnostics cannot be performed When CC-Link IE TSN/CC-Link IE Field diagnostics cannot be performed with the engineering tool in CC-Link IE TSN communication mode, check the following items. Check item Action Is the DATA LINK LED of the FPGA module on? Check the DATA LINK LED of the FPGA module, and if it is not on, perform the following troubleshooting.
Page 444 When unable to communicate with the FPGA Module Configuration Tool When unable to communicate with the FPGA Module Configuration Tool, check the following items. Check item Action Is the FPGA module powered off? Confirm that the FPGA module is powered on. Is a Ethernet cable connected to a personal Check if the Ethernet cable is properly connected.
Page 445: Chapter 21 Troubleshooting During Fpga Development
Using a difference check tool, check if there are any differences between the RTL downloaded from the Mitsubishi Electric FA site and the RTL for which FPGA logic synthesis is performed. Is there any problem with FPGA design and verification? Please review the FPGA design/verification performed by the customer.
Page 446 MEMO 21 TROUBLESHOOTING DURING FPGA DEVELOPMENT...
Page 447: Chapter 22 Trouble Examples Of Dc Input/Output
TROUBLE EXAMPLES of DC INPUT/OUTPUT 22.1 Troubles and Countermeasures for DC Input Circuits Examples of troubles in the DC input circuit and countermeasures are shown below. An input signal does not turn off No.1 ■Cause Drive by a switch with LED indicator DC input (sink) FPGA module...
Page 448 When the resistor (R) is 1.3k, for example, the power capacity (W) of the resistor (R) becomes 0.638W.  28.8  1300 = 0.638W W = (input voltage) Because the resistor requires a power capacity that is 3 to 5 times larger than the actual current consumption, the resistor connected to the terminal should be 1.3k...
Page 449 A signal incorrectly inputs data ■Cause • Noise is taken as input data. • The filter settings are incorrect. ■Action • To prevent excessive noise, avoid installing power cables together with I/O cables. (150mm or more, as a guide) • Check settings such as filter settings. •...
Page 450: Troubles And Countermeasures For Dc Output Circuits
22.2 Troubles and Countermeasures for DC Output Circuits Examples of troubles in DC output (transistor (sink) output) circuits and countermeasures are shown below. A load momentarily turns on from off when the system is powered off ■Cause When an inductive load is connected, [2] Load may turn on from off due to a diversion of back electromotive force at [1] Shutoff.
Page 451 When an output terminal is off, the LED connected as a load dimly turns on ■Cause The load operates by the leakage current when the output module is off. FPGA module Action DC output (sink output) 24VDC power supply ■Action Connect a resistor of 5 to 50k...
Page 452: Chapter 23 Check/Clear Error Codes
CHECK/CLEAR ERROR CODES 23.1 Checking Error Codes Error codes can be checked by any of the following methods: • Checking with the FPGA Module Configuration Tool ( Page 121 Module diagnostics) • Checking by using CC-Link IE TSN/CC-Link IE Field diagnostics (in CC-Link IE TSN communication mode) ( Page 450 Checking by using CC-Link IE TSN/CC-Link IE Field diagnostics) •...
Page 453 Operating procedure Connect the engineering tool to the CPU module. Start CC-Link IE TSN/CC-Link IE Field diagnostics from the menu. [Diagnostics]  [CC-Link IE TSN/CC-Link IE Field Diagnostic] Right-click the device station whose error history is to be checked, and select "Error/Event History". Follow the on-screen instructions and click the [Yes] button.
Page 454: Clearing Error Codes
23.2 Clearing Error Codes The clearing method differs depending on the classification of each error. Classification How to clear an error Major An error cannot be cleared. Moderate Whether an error can be cleared depends on what the error is. ( Page 450 CHECK/CLEAR ERROR CODES) For an error code that can be cleared, clear the error after correcting the cause of the error.
Page 455: Chapter 24 Error Code List
ERROR CODE LIST The error codes are classified into the following three types. Classification Description Major error An error that cannot be recovered. The RUN LED turns off. Moderate error An error where the module can continue to operate but FPGA control cannot continue. The ERR. LED turns on. Minor error Module-specific An error where the module and FPGA control can continue to operate.
Page 456 Error code Classification Error name Description and cause Action (hexadecimal) 1063H Minor Competing access Parameter saving has been executed by • If this error has occurred, the parameter to non-volatile turning on Parameter save request (RY2) value that was attempted to be saved by memory while the parameter write (memory + non- Parameter save request (RY2) is not...
Page 457 Error code Classification Error name Description and cause Action (hexadecimal) 1210H Minor Time setting error The time setting request was issued while Set values that satisfy all of the following a value set for Time information is in any of and execute the time setting again.
Page 458 Error code Classification Error name Description and cause Action (hexadecimal) 1403H Minor FTP file generation File generation in the FTP server failed. • The specified file may be used in another error process in the FTP server. Wait for a while and perform the operation again.
Page 459 Error code Classification Error name Description and cause Action (hexadecimal) 2011H Moderate Non-volatile The IP address and subnet mask stored in • The module will be automatically memory data error the non-volatile memory are abnormal. recovered immediately after the error (IP address) occurs.
Page 460 Error code Classification Error name Description and cause Action (hexadecimal) 302H Moderate Filter sampling The value of Filter sampling pulse ■For DC input pulse (E) setting (E)(FPGA register address: 1000_2008H • Set Filter sampling pulse (E) (FPGA error to 1000_200CH) is invalid. register address: 1000_2008H to ■For DC input 1000_200CH) to Data sampling timing...
Page 461 Error code Classification Error name Description and cause Action (hexadecimal) 311H Moderate Output signal/Input A value other than Register setting value Set Output signal/Input/output direction output direction (0H) and User circuit output (3H) is set for signal selection (E) (address: signal selection Output signal/Input output direction signal 1000_5028H to 1000_502CH) to Register...
Page 462 Error code Classification Error name Description and cause Action (hexadecimal) 3C00H Major Hardware error Module hardware error • Power off and on the module power supply. • If this error occurs again, the possible cause is a module failure. Please consult your local Mitsubishi representative.
Page 463 Communication system error codes Error code Classification Error name Description and cause Action (hexadecimal) *1*2 D000H Minor Communication Invalid network settings are received. • Power off and on the module power setting error 1 supply. • If this error occurs again, the possible cause is a module failure.
Page 464 Error code Classification Error name Description and cause Action (hexadecimal) *1*2 D028H Minor Communication The communication cycle that cannot be Correct the communication cycle setting so cycle setting error handled by the FPGA module is set while that the FPGA module can operate with the (CC-Link IE TSN the FPGA module is operating with CC- set communication cycle.
Page 465: Appendices
APPENDICES Appendix 1 Remote I/O Signal Remote input (RX) is a signal that indicates the state of the FPGA module (such as control state and external input state). In the CC-Link IE TSN communication mode, it is an input signal from the FPGA module to the master module. In addition, regardless of the operation mode setting, it can be referenced by an external device via SLMP communication.
Page 466 NZ2GN2S-D41P01 Remote input signals Name Remote output signals Name Device number Device number RX10 External input signal X0(B0) RY10 External output signal Y0(B0) RX11 External input signal X1(B0) RY11 External output signal Y1(B0) RX12 External input signal X2(B0) RY12 External output signal Y2(B0)
Page 467 NZ2GN2S-D41D01 Remote input signals Name Remote output signals Name Device number Device number RX10 External input signal X0(B0) RY10 External output signal Y0(B0) RX11 External input signal X1(B0) RY11 External output signal Y1(B0) RX12 External input signal X2(B0) RY12 External output signal Y2(B0) RX13 External input signal X3(B0) RY13...
Page 468 NZ2GN2S-D41PD02 Remote input signals Name Remote output signals Name Device number Device number RX10 External input signal X0(B0) RY10 External output signal Y0(B0) RX11 External input signal X1(B0) RY11 External output signal Y1(B0) RX12 External input signal X2(B0) RY12 External output signal Y2(B0) RX13 External input signal X3(B0) RY13...
Page 469 NZ2EX2S-D41P01 Remote input signals Name Remote output signals Name Device number Device number RX40 External input signal X0 (E0) RY40 External output signal Y0(E0) RX41 External input signal X1 (E0) RY41 External output signal Y1(E0) RX42 External input signal X2 (E0) RY42 External output signal Y2(E0) RX43...
Page 470 NZ2EX2S-D41D01 Remote input signals Name Remote output signals Name Device number Device number RX40 External input signal X0 (E0) RY40 External output signal Y0(E0) RX41 External input signal X1 (E0) RY41 External output signal Y1(E0) RX42 External input signal X2 (E0) RY42 External output signal Y2(E0) RX43...
Page 471: Details Of Remote Input Signals
Details of remote input signals FPGA controlling flag ■Device number Name Device number FPGA controlling flag ■Description The FPGA controlling flag (RX0) turns on while the FPGA is operating. This signal turns on under the following conditions. • When FPGA control start request (RY0) turns on •...
Page 472 Parameter saving completion flag ■Device number Name Device number Parameter saving completion flag ■Description Turns on when a parameter is saved in non-volatile memory by turning on Parameter save request (RY2). Use as an interlock to turn on and off Parameter save request (RY2). For details on parameters, refer to the following.
Page 473 Logging start flag ■Device number Name Device number Logging start flag ■Description Turns on when starting the logging or transferring logging data to the FTP server by turning on Logging start request (RY3). Use as an interlock to turn on and off Logging start request (RY3). This signal turns on in the following conditions.
Page 474 ■Logging data re-transfer Logging start flag (RX3) Logging start request (RY3) FTP resend allowed (RY4) FTP transfer completion flag (RX4) Logging operation state monitor (RWrB) Performed by FPGA module Executed by the program (1) FTP transfer start waiting (5H) (2) FTP transferring (4H) (3) Collection start waiting (1H) APPX Appendix 1 Remote I/O Signal...
Page 475 FTP transfer completion flag ■Device number Name Device number FTP transfer completion flag ■Description Turns on when the logging data transfer to the FTP server is completed successfully or with an error. Successful completion and error completion can be verified with FTP transfer error completion flag (RX5). •...
Page 476 FTP transfer error completion flag ■Device number Name Device number FTP transfer error completion flag ■Description Turns on when the transfer of logging data to the FTP server is completed with an error. For details, refer to the following. Page 473 FTP transfer completion flag FPGA control stop while data collection flag ■Device number Name...
Page 477 Logging control suspension flag ■Device number Name Device number Logging control suspension flag ■Description Use as an interlock to turn on and off the logging control suspend request (RY7) used to stop the logging data collection or FTP transfer. This signal turns on under the following conditions. •...
Page 478 Error flag ■Device number Name Device number Error flag ■Description Error flag (RXA) turns on when an error occurs. To clear the Error flag (RXA) and the latest error code (RWr0), turn the error clear request (RYA) on and off. ■When a minor error occurs Latest error code (RWr0) 0000H...
Page 479 Remote READY ■Device number Name Device number Remote READY ■Description Remote READY (RXB) turns on after the module power supply is turned on. Use as an interlock to read and write remote I/O signals, remote register areas, and remote buffer memory from the master module or SLMP-compatible device.
Page 480 External input signal XY (B0 to B2, E0 to E2) ■Device number Name Device number External input signal XY (B0 to B2, E0 to E2) RX18, RX28, RX38, RX48, RX58, RX68 • The allocation differs depending on the mounted module. ( Page 463 List of remote I/O signals) •...
Page 481: Details Of Remote Output Signals
Details of remote output signals FPGA control start request ■Device number Name Device number FPGA control start request ■Description Use to start FPGA control. If FPGA controlling flag (RX0) is OFF, FPGA control is stopped. Turning on FPGA control start request (RY0) starts FPGA control. When FPGA control automatic start setting is set to "Enable", FPGA control starts automatically when the module power supply is turned on.
Page 482 Parameter save request ■Device number Name Device number Parameter save request ■Description Turning on the FPGA parameter save request (RY2) saves the current FPGA module parameters in non-volatile memory. For the timing of turning on and off FPGA parameter save request (RY2), refer to the following. Page 470 Parameter saving completion flag For the parameter area, refer to the following.
Page 483 FTP resend allowed ■Device number Name Device number FTP resend allowed ■Description Specify whether to re-transfer logging data to the FTP server when the following occurs. An FTP communication error occurred while transferring logging data to the FTP server. Turn on Logging control suspend request (RY7) during logging data transfer. FPGA control was stopped while collecting logging data.
Page 484 Logging control suspend request ■Device number Name Device number Logging control suspend request ■Description Use to stop collecting logging data or transferring logging data to the FTP server. For the timing of turning on and off Logging control suspension flag (RX7), refer to the following. Page 475 Logging control suspension flag Error clear request flag ■Device number...
Page 485 External output signal Y0 to YF(B0 to B2, E0 to E2) ■Device number Name Device number External output signal Y0 to YF(B0 to B2, E0 to E2) RY10 to RY6F The external output signal corresponding to the remote output signal (RY) differs depending on the FPGA module model.
Page 486 External output signal XY(B0 to B2, E0 to E2) ■Device number Name Device number External output signal XY(B0 to B2, E0 to E2) RY18, RY28, RY38, RY48, RY58, RY68 The external output signal corresponding to the remote output signal (RY) differs depending on the FPGA module model.
Page 487: Appendix 2 Remote Register
Appendix 2 Remote Register Remote register (RWr) is the state of FPGA module (error, logging, user circuit). In CC-Link IE TSN communication mode, the master module receives Remote register (RWr) from FPGA module. Also, Remote register (RWr) can be received from an external device via SLMP communication regardless of the operation mode setting.
Page 488: Details Of Remote Registers
Details of remote registers Latest error code ■Device number Name Device number Latest error code RWr0 ■Description The error code is stored when an error occurs. This register is cleared when Error clear request flag (RYA) is turned on after removing the cause of the error that occurred.
Page 489 Sampling count monitor ■Device number Name Device number Sampling count monitor RWrC, RWrD ■Description Stores the number of times logging data was sampled after logging started. The value is cleared to 0 when logging starts and is incremented by 1 at each sampling. It does not count up beyond 4294967295 (FFFFFFFFH).
Page 490: Appendix 3 Remote Buffer Memory
Appendix 3 Remote Buffer Memory Describes the remote buffer memory. The SLMP command and dedicated instructions (REMTO, REMTOD, REMTOIP, REMTODIP, REMFR, REMFRD, REMFRIP, and REMFRDIP instructions) can be used to read from and write to the remote buffer memory. For the dedicated instructions, refer to the following. ...
Page 491 ■DAC CH0 (E0) setting parameter to DAC CH1 (E2) setting parameter : Applicable, : Not applicable Address Name Default Read Write value Hexadecimal Decimal 0600H 1536 Use prohibited      0601H 1537 DAC offset CH0(E0) 8000H 0602H 1538 DAC range setting CH0(E0) 0003H...
Page 492 FPGA register access area ■FPGA register write : Applicable, : Not applicable Address Name Default Read Write value Hexadecimal Decimal 1200H, 1201H 4608, 4609 Write start address 0000H     1202H 4610 Write size 0000H   1203H 4611 Write request 0000H...
Page 493: Details Of Remote Buffer Memory
Details of remote buffer memory This section describes the details of remote buffer memory addresses of FPGA module. User switch enable/disable ■Address Name Remote buffer memory address User switch enable/disable 04D0H ■Description Enables or disables USER switch (function setting switch 7) to USER switch (function setting switch 10). 0 (fixed) (1) USER switch 0: Disable (Default)
Page 494 FPGA control automatic start delay setting ■Address Name Remote buffer memory address FPGA control automatic start delay setting 04D2H ■Description Sets the time from FPGA configuration completion until the automatic start of FPGA control. ■Setting range 0 to 255[s] (Default: 0) When the value outside of the setting range is specified, the FPGA module works as 255.
Page 495 FPGA control continuation setting ■Address Name Remote buffer memory address FPGA control continuation setting 04D4H ■Description Sets whether to stop or continue FPGA control when the data link with the CPU module and master station is broken during FPGA module operation in CC-Link IE TSN communication mode. 0 (fixed) (1) FPGA control 0: Stop (default)
Page 496 DAC range setting ■Address Name Remote buffer memory address DAC range setting CH0(E0) 0602H DAC range setting CH1(E0) 0606H DAC range setting CH0(E1) 060AH DAC range setting CH1(E1) 060EH DAC range setting CH0(E2) 0612H DAC range setting CH1(E2) 0616H ■Description Sets the DAC output range.
Page 497 Function setting switch state monitor ■Address Name Remote buffer memory address Function setting switch state monitor 0902H ■Description The ON/OFF status of function setting switches 1 to 10 can be checked. At what point ON, OFF status is displayed differs depending on the function setting switch. •...
Page 498 Parameter initialization command ■Address Name Remote buffer memory address Parameter initialization command 1000H ■Description This command resets parameters stored in the remote buffer memory, FPGA register, and non-volatile memory to the default values. When non-volatile memory data error (parameter) (error code: 2010H) occurs, the FPGA module can be restored. When the parameter initialization command (remote buffer memory address 1000H) is set to Commanded (1), parameters are initialized.
Page 499 Write start address ■Address Name Remote buffer memory address Write start address 1200H, 1201H ■Description When writing the value stored in the write data  (remote buffer memory address: 1204H to 1383H) to an FPGA register, set the start address of the FPGA register to be written. For the writable range, refer to the following.
Page 500 Write request ■Address Name Remote buffer memory address Write request 1203H ■Description After setting Write start address (remote buffer memory address: 1200H, 1201H) and the write size (remote buffer memory address: 1202H), set this remote buffer memory to Requested (1H). The value of the write data  (remote buffer memory address: 1204H to 1383H) will be stored in the set FPGA register.
Page 501 Read size ■Address Name Remote buffer memory address Read size 1402H ■Description Sets the address range of the FPGA register to be read in units of words. For the readable range, refer to the following. Page 324 Method using remote buffer memory ■Setting range The setting range is from 1 to 384.
Page 502 Time information set ■Address Name Remote buffer memory address Time information set 1600H ■Description Time information set is used to reflect the values set below to logging data during logging and time information of error history while operating in standalone mode. •...
Page 503 Time information (month, day, hour) ■Address Name Remote buffer memory address Time information (month, day, hour) 1602H ■Description Sets the time information (month, day, hour) to be reflected in the logging data and error history. 0 (fixed) Month Hour ■Setting range •...
Page 504: Appendix 4 Fpga Register
Appendix 4 FPGA register Describes FPGA register areas. Precautions Read-only bits: Invalid when writing. Write-only bits: Fixed to 0 when read. For the types of each register, refer to the following. Page 503 List of FPGA register areas There are restrictions on setting values for parameter register areas. Check the notes and restrictions in the FPGA register details. Setting value restrictions are checked by firmware at the start of FPGA control and when the parameter save request (RY2) is turned on, and a moderate error may occur in the module depending on the conflicting restrictions.
Page 505: List Of Fpga Register Areas
List of FPGA register areas A list of FPGA register assignments is shown below. Reset control part : Applicable, : Not applicable FPGA register address Register name Description Type Read Write    1000_0002H mode_ctrl2 Internal operation start/stop  ...
Page 506 Digital input control part : Applicable, : Not applicable FPGA register Register name Description Type Read Write address 1000_3000H iport_iob0_0_filcnt_upper Input filter counter upper limit (IOB0_X0)(B0) Parameter   1000_3002H iport_iob0_1_filcnt_upper Input filter counter upper limit (IOB0_X1)(B0) Parameter   1000_3004H iport_iob0_2_filcnt_upper Input filter counter upper limit (IOB0_X2)(B0)
Page 507 FPGA register Register name Description Type Read Write address 1000_3062H iport_ioe0_1_filcnt_upper Input filter counter upper limit (IOE0_X1)(E0) Parameter     1000_3064H iport_ioe0_2_filcnt_upper Input filter counter upper limit (IOE0_X2)(E0) Parameter   1000_3066H iport_ioe0_3_filcnt_upper Input filter counter upper limit (IOE0_X3)(E0) Parameter 1000_3068H iport_ioe0_4_filcnt_upper...
Page 508 FPGA register Register name Description Type Read Write address 1000_3114H iport_ioe2x_monitor Input signal monitor (E2) Monitor   Digital output control part : Applicable, : Not applicable FPGA register Register name Description Type Read Write address   1000_4000H oport_iob0y_osel Output signal selection (B0) Parameter ...
Page 509 FPGA register Register name Description Type Read Write address 1000_5024H ioport_iob2_dio485_osel Output signal/Input output direction signal selection (B2) Parameter   1000_5026H Reserve   1000_5028H ioport_ioe0_dio485_osel Output signal/Input output direction signal selection (E0) Parameter 1000_502AH ioport_ioe1_dio485_osel Output signal/Input output direction signal selection (E1) Parameter ...
Page 510 FPGA register address Register name Description Type Read Write   1000_6052H aiport_ade2_1_result A/D conversion value CH1 (E2) Monitor   1000_6054H aiport_ade2_2_result A/D conversion value CH2 (E2) Monitor   1000_6056H aiport_ade2_3_result A/D conversion value CH3 (E2) Monitor  ...
Page 511 Analog output control part : Applicable, : Not applicable FPGA register address Register name Description Type Read Write 1000_7000H aoport_da_start D/A conversion enable/disable setting Parameter     1000_7002H aoport_da_data_sel D/A conversion value selection Parameter 1000_7004H aoport_da_cyc_sel D/A conversion timing selection Parameter ...
Page 512 User circuit part register (Write data) : Applicable, : Not applicable FPGA Register Description Type Read Write register name address   1000_B000H usr_wreg_000 Digital control part enable/disable control register (IOB0_X0 B0) Parameter   1000_B002H usr_wreg_001 Digital control part enable/disable control register (IOB0_X1 B0) Parameter ...
Page 513 FPGA Register Description Type Read Write register name address   1000_B078H usr_wreg_03C Digital control part enable/disable control register (IOE0_X0 E0) Parameter   1000_B07AH usr_wreg_03D Digital control part enable/disable control register (IOE0_X1 E0) Parameter 1000_B07CH usr_wreg_03E Digital control part enable/disable control register (IOE0_X2 E0) Parameter ...
Page 514 FPGA Register Description Type Read Write register name address   1000_B0F6H usr_wreg_07B Digital output control digital output selection (E0) Parameter   1000_B0F8H usr_wreg_07C Digital output control digital output selection (E1) Parameter   1000_B0FAH usr_wreg_07D Digital output control digital output selection (E2) Parameter ...
Page 515 FPGA Register Description Type Read Write register name address   1000_B1AAH usr_wreg_0D5 Counter control part 32-bit ring counter (1-phase multiple of 1) input signal Parameter/ selection (B0) Control   1000_B1B6H usr_wreg_0DB Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit Parameter value (lower side) (B1) 1000_B1B8H...
Page 516 FPGA Register Description Type Read Write register name address   1000_B258H usr_wreg_12C Pulse output part output pulse count upper limit value (upper side) (E2) Parameter   1000_B260H usr_wreg_130 Pulse output part pulse output selection 0 (B0) Parameter  ...
Page 517 FPGA Register Description Type Read Write register name address   1000_B322H usr_wreg_191 Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction Control (E0)   1000_B324H usr_wreg_192 Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower Control side) (E0) 1000_B326H...
Page 518 FPGA Register Description Type Read Write register name address   1000_B378H usr_wreg_1BC Pulse output part pulse output enable (E1) Control   1000_B37AH usr_wreg_1BD Pulse output part pulse output enable (E2) Control   1000_B380H usr_wreg_1C0 Analog output part D/A conversion value CH0 (E0) Control ...
Page 519 FPGA Register Description Type Read Write register name address   1000_BB40H usr_rreg_1A0 Analog control A/D conversion value CH5 (E1) Monitor   1000_BB42H usr_rreg_1A1 Analog control A/D conversion value CH6 (E1) Monitor 1000_BB44H usr_rreg_1A2 Analog control A/D conversion value CH7 (E1) Monitor ...
Page 520 FPGA Register Description Type Read Write register name address   1000_BB8AH usr_rreg_1C5 Counter control part 32-bit ring counter (1-phase multiple of 1) counter value (lower Monitor side) (E0)   1000_BB8CH usr_rreg_1C6 Counter control part 32-bit ring counter (1-phase multiple of 1) counter value Monitor (upper side) (E0) ...
Page 521: Fpga Register Details (Reset Control Part)
FPGA register details (reset control part) The details of the FPGA register of the reset control part are shown below. Internal operation start/stop ■Address Name FPGA register address Internal operation start/stop (mode_ctrl2) 1000_0002H ■Description Use for FPGA internal operation start/stop. Firmware controls the FPGA control start processing and FPGA control stop processing.
Page 522 Module type (extension) ■Address Name FPGA register address Module type (extension) (unit_set_ext) 1000_0006H ■Description Stores the module type of the circuit board connected to the connector (E0 to E2) of the extension module. 0 (fixed) (1) Module type (E0 to E2) (IOE_UNIT[4:0]) •...
Page 523 External reset ON/OFF setting ■Address Name FPGA register address If the external reset ON/OFF setting (ioport_set) 1000_0020H ■Description Sets ON (issued) or OFF (not issued) for the reset issued to the circuit board when FPGA control is stopped (when the internal operation start/stop is stop).
Page 524 FPGA version register ■Address Name FPGA register address FPGA version register (fpga_version) 1000_0100H ■Description The version of the standard circuit and sample circuit can be checked. • 0001H: Version 1.00 ■FPGA initial value FPGA version ■Firmware initial value  ■Reset cause Reset APPX Appendix 4 FPGA register...
Page 525: Fpga Register Details (Timing Generator)
FPGA register details (timing generator) The details of the FPGA register of the timing generator are shown below. Filter sampling pulse ■Address Name FPGA register address Filter sampling pulse (B0) (tim_iob0x_samp) 1000_2000H Filter sampling pulse (B1) (tim_iob1x_samp) 1000_2002H Filter sampling pulse (B2) (tim_iob2x_samp) 1000_2004H Filter sampling pulse (E0) (tim_ioe0x_samp) 1000_2008H...
Page 526 Data sampling timing (B) ■Address Name FPGA register address Data sampling timing (B0) (tim_iob0x_en) 1000_2100H Data sampling timing (B1) (tim_iob1x_en) 1000_2102H Data sampling timing (B2) (tim_iob2x_en) 1000_2104H ■Description Sets the timing (cycle) for sampling DC/differential (RS-422/RS-485). (Setting unit: 0.01s) • FFFFH: 655.36s •...
Page 527 Data sampling timing (E) ■Address Name FPGA register address Data sampling timing (E0) (tim_ioe0x_en) 1000_2108H Data sampling timing (E1) (tim_ioe1x_en) 1000_210AH Data sampling timing (E2) (tim_ioe2x_en) 1000_210CH ■Description Sets the timing (cycle) for sampling DC/differential (RS-422/RS-485)/analog input. (Setting unit: 0.01s) •...
Page 528 Data update timing ■Address Name FPGA register address Data update timing (B0) (tim_iob0x_conv) 1000_2110H Data update timing (B1) (tim_iob1x_conv) 1000_2112H Data update timing (B2) (tim_iob2x_conv) 1000_2114H Data update timing (E0) (tim_ioe0x_conv) 1000_2118H Data update timing (E1) (tim_ioe1x_conv) 1000_211AH Data update timing (E2) (tim_ioe2x_conv) 1000_211CH ■Description Sets the output timing (cycle) for DC/differential (RS-422/RS-485)/analog output.
Page 529 Logging cycle timing ■Address Name FPGA register address Logging cycle timing (tim_log_cyc) 1000_2200H ■Description Sets the logging cycle timing. • FFFFH: 32.768ms • FFFEH: 32.7675ms to 0003H: 2s • 0002H: 1.5s • 0000H to 0001H: 1s ■FPGA initial value 0000H ■Firmware initial value 0001H ■Reset cause...
Page 530: Fpga Register Details (Digital Input Control Part)
FPGA register details (digital input control part) The details of the FPGA register of the digital input control part are shown below. Input filter counter upper limit ■Address Name FPGA register address Input filter counter upper limit (IOB0_X0)(B0) (iport_iob0_0_filcnt_upper) to Input filter counter upper limit (IOB0_XF)(B0) 1000_3000H to 1000_301EH (iport_iob0_f_filcnt_upper) Input filter counter upper limit (IOB1_X0)(B1) (iport_iob1_0_filcnt_upper) to Input filter counter upper limit (IOB1_XF)(B1)
Page 531 ■Precautions and restrictions • When a differential I/O circuit board is connected to B, the input filter counter upper limit (IOB_X8)(B) (iport_iob_8_filcnt_upper) to input filter counter upper limit (IOB_XF)(B) (iport_iob_f_filcnt_upper) settings are disabled. • When a differential I/O circuit board is connected to E, the input filter counter upper limit (IOE_X8)(E) (iport_ioe_8_filcnt_upper) to input filter counter upper limit (IOE_XF)(E) (iport_ioe_f_filcnt_upper) settings are disabled.
Page 532: Fpga Register Details (Digital Output Control Part)
FPGA register details (digital output control part) Output signal selection ■Address Name FPGA register address Output signal selection (B0) (oport_iob0y_osel) 1000_4000H Output signal selection (B1) (oport_iob1y_osel) 1000_4002H Output signal selection (B2) (oport_iob2y_osel) 1000_4004H Output signal selection (E0) (oport_ioe0y_osel) 1000_4008H Output signal selection (E1) (oport_ioe1y_osel) 1000_400AH Output signal selection (E2) (oport_ioe2y_osel) 1000_400CH...
Page 533 Output value setting register ■Address Name FPGA register address Output value setting (B0) (oport_iob0y_odata) 1000_4010H Output value setting (B1) (oport_iob1y_odata) 1000_4012H Output value setting (B2) (oport_iob2y_odata) 1000_4014H Output value setting (E0) (oport_ioe0y_odata) 1000_4018H Output value setting (E1) (oport_ioe1y_odata) 1000_401AH Output value setting (E2) (oport_ioe2y_odata) 1000_401CH ■Description Sets the signal value to be output to the output signal (IOB_Yx) and the output signal (IOE_Yx).
Page 534 Output signal monitor register ■Address Name FPGA register address Output signal monitor (B0) (iport_iob0y_monitor) 1000_4020H Output signal monitor (B1) (iport_iob1y_monitor) 1000_4022H Output signal monitor (B2) (iport_iob2y_monitor) 1000_4024H Output signal monitor (E0) (iport_ioe0y_monitor) 1000_4030H Output signal monitor (E1) (iport_ioe1y_monitor) 1000_4032H Output signal monitor (E2) (iport_ioe2y_monitor) 1000_4034H ■Description The output signals (IOB0_Y0 to IOB0_YF) after output signal selection (after selecting with the oport_iob0y_osel register) to...
Page 535 Differential output HOLD/CLEAR ■Address Name FPGA register address Differential output HOLD/CLEAR (B0) (oport_iob0y_holdclr) 1000_4040H Differential output HOLD/CLEAR (B1) (oport_iob1y_holdclr) 1000_4042H Differential output HOLD/CLEAR (B2) (oport_iob2y_holdclr) 1000_4044H Differential output HOLD/CLEAR (E0) (oport_ioe0y_holdclr) 1000_4046H Differential output HOLD/CLEAR (E1) (oport_ioe1y_holdclr) 1000_4048H Differential output HOLD/CLEAR (E2) (oport_ioe2y_holdclr) 1000_404AH ■Description Fix the logic of output signals (IOB0_Y0 to IOB0_Y7) to output signals (IOE2_Y0 to IOE2_Y7) when b0 of internal operation...
Page 536: Fpga Register Details (Digital I/O Control Part)
FPGA register details (digital I/O control part) Input filter counter upper limit ■Address Name FPGA register address Input filter counter upper limit (IOB0_DIO485_I)(B0) (iport_iob0_dio485_filcnt_upper) 1000_5000H Input filter counter upper limit (IOB1_DIO485_I)(B1) (iport_iob1_dio485_filcnt_upper) 1000_5002H Input filter counter upper limit (IOB2_DIO485_I)(B2) (iport_iob2_dio485_filcnt_upper) 1000_5004H Input filter counter upper limit (IOE0_DIO485_I)(E0) (iport_ioe0_dio485_filcnt_upper) 1000_5008H...
Page 537 I/O signal monitor ■Address Name FPGA register address I/O signal monitor (IOB0_DIO485)(B0) (ioport_iob0_dio485_monitor) 1000_5010H I/O signal monitor (IOB1_DIO485)(B1) (ioport_iob1_dio485_monitor) 1000_5012H I/O signal monitor (IOB2_DIO485)(B2) (ioport_iob2_dio485_monitor) 1000_5014H I/O signal monitor (IOE0_DIO485)(E0) (ioport_ioe0_dio485_monitor) 1000_5018H I/O signal monitor (IOE1_DIO485)(E1) (ioport_ioe1_dio485_monitor) 1000_501AH I/O signal monitor (IOE2_DIO485)(E2) (ioport_ioe2_dio485_monitor) 1000_501CH ■Description Monitors input signals (IOB_DIO485_I, IOE_DIO485_I) after filtering, and output signals (IOB_DIO485_O,...
Page 538 Select output signal or I/O direction signal ■Address Name FPGA register address Output signal/Input output direction signal selection (B0) (ioport_iob0_dio485_osel) 1000_5020H Output signal/Input output direction signal selection (B1) (ioport_iob1_dio485_osel) 1000_5022H Output signal/Input output direction signal selection (B2) (ioport_iob2_dio485_osel) 1000_5024H Output signal/Input output direction signal selection (E0) (ioport_ioe0_dio485_osel) 1000_5028H Output signal/Input output direction signal selection (E1) (ioport_ioe1_dio485_osel) 1000_502AH...
Page 539 Output value/Input output direction setting ■Address Name FPGA register address Output value/Input output direction setting (B0) (ioport_iob0_dio485_odata) 1000_5030H Output value/Input output direction setting (B1) (ioport_iob1_dio485_odata) 1000_5032H Output value/Input output direction setting (B2) (ioport_iob2_dio485_odata) 1000_5034H Output value/Input output direction setting (E0) (ioport_ioe0_dio485_odata) 1000_5038H Output value/Input output direction setting (E1) (ioport_ioe1_dio485_odata) 1000_503AH...
Page 540 Differential output HOLD/CLEAR ■Address Name FPGA register address Differential output HOLD/CLEAR (IOB0_DIO485_O) (B0) (ioport_iob0y_holdclr) 1000_5040H Differential output HOLD/CLEAR (IOB1_DIO485_O) (B1) (ioport_iob1y_holdclr) 1000_5042H Differential output HOLD/CLEAR (IOB2_DIO485_O) (B2) (ioport_iob2y_holdclr) 1000_5044H Differential output HOLD/CLEAR (IOE0_DIO485_O) (E0) (ioport_ioe0y_holdclr) 1000_5046H Differential output HOLD/CLEAR (IOE1_DIO485_O) (E1) (ioport_ioe1y_holdclr) 1000_5048H Differential output HOLD/CLEAR (IOE2_DIO485_O) (E2) (ioport_ioe2y_holdclr) 1000_504AH...
Page 541: Fpga Register Details (Analog Input Control Part)
FPGA register details (analog input control part) A/D conversion enable/disable setting ■Address Name FPGA register address A/D conversion enable/disable setting (aiport_ad_start) 1000_6000H ■Description Enable or disable A/D conversion. The firmware sets the A/D conversion enable/disable setting value to A/D conversion start as FPGA control start processing, and A/D conversion starts.
Page 542 A/D conversion timing selection ■Address Name FPGA register address A/D conversion timing selection (aiport_ad_cyc_sel) 1000_6002H ■Description Select the A/D conversion timing of ADC. 0 (fixed) (1) A/D conversion timing selection (E0) • 1: User circuit output • 0: Data sampling timing (2) A/D conversion timing selection (E1) •...
Page 543 ADC voltage/current input setting ■Address Name FPGA register address ADC voltage/current input setting (E0) (aiport_ade0_vi_set) 1000_6008H ADC voltage/current input setting (E1) (aiport_ade1_vi_set) 1000_600AH ADC voltage/current input setting (E2) (aiport_ade2_vi_set) 1000_600CH ■Description Set the ADC voltage/current range for each CH. The firmware automatically performs the settings according to the ADC range setting CH0 to 3 (E0) (aiport_ade0_0-3_range) (FPGA register address: 1000_6100H) to ADC range setting CH8 to B (E2) (aiport_ade2_8-B_range) (FPGA register address: 1000_6110H).
Page 544 ADC range setting ■Address Name FPGA register address ADC range setting CH0 to 3 (E0) (aiport_ade0_0-3_range) 1000_6100H ADC range setting CH4 to 7 (E0) (aiport_ade0_4-7_range) 1000_6102H ADC range setting CH8 to B (E0) (aiport_ade0_8-B_range) 1000_6104H ADC range setting CH0 to 3 (E1) (aiport_ade1_0-3_range) 1000_6106H ADC range setting CH4 to 7 (E1) (aiport_ade1_4-7_range) 1000_6108H...
Page 545 ADC oversampling ratio setting ■Address Name FPGA register address ADC oversampling ratio setting (E0) (aiport_ade0_oversamp) 1000_6120H ADC oversampling ratio setting (E1) (aiport_ade1_oversamp) 1000_6122H ADC oversampling ratio setting (E2) (aiport_ade2_oversamp) 1000_6124H ■Description Sets the ADC oversampling ratio. 0 (fixed) (1) ADC oversampling ratio setting (E) •...
Page 546 ADC offset setting value ■Address Name FPGA register address ADC offset setting value CH0 to 1 (E0) (aiport_ade0_0-1_offset) to ADC offset setting value CHA to B (E0) (aiport_ade0_a- 1000_6160H to 1000_616AH b_offset) ADC offset setting value CH0 to 1 (E1) (aiport_ade1_0-1_offset) to ADC offset setting value CHA to B (E1) (aiport_ade1_a- 1000_616CH to 1000_6176H b_offset) ADC offset setting value CH0 to 1 (E2) (aiport_ade2_0-1_offset) to ADC offset setting value CHA to B (E2) (aiport_ade2_a-...
Page 547: Fpga Register Details (Analog Output Control Part)
FPGA register details (analog output control part) D/A conversion enable/disable setting ■Address Name FPGA register address D/A conversion enable/disable setting (aoport_da_start) 1000_7000H ■Description Enables or disables D/A conversion. The firmware reads this setting during FPGA control start processing and sets the DAC. 0 (fixed) (1) CH0 D/A conversion enable/disable setting (E0) •...
Page 548 D/A conversion value selection ■Address Name FPGA register address D/A conversion value selection (aoport_da_data_sel) 1000_7002H ■Description Selects the D/A conversion value to output to DAC. 0 (fixed) (1) CH0 D/A conversion value setting selection (E0) • 1: User circuit output •...
Page 549 D/A conversion timing selection ■Address Name FPGA register address D/A conversion timing selection (aoport_da_cyc_sel) 1000_7004H ■Description Selects the D/A conversion timing of DAC. 0 (fixed) (1) D/A conversion timing selection (E0) • 1: User circuit output • 0: Data update timing (2) D/A conversion timing selection (E1) •...
Page 550 DAC LDAC signal selection ■Address Name FPGA register address DAC LDAC signal selection (aoport_da_ldac_sel) 1000_7006H ■Description Selects the LDAC signal to output to DAC. 0 (fixed) (1) CH0 DAC LDAC signal selection (E0) • 1: User circuit output • 0: Fixed to Low (2) CH1 DAC LDAC signal selection (E0) •...
Page 551 D/A conversion value ■Address Name FPGA register address D/A conversion value CH0 (E0) (aoport_dae0_0_data) 1000_7100H D/A conversion value CH1 (E0) (aoport_dae0_1_data) 1000_7102H D/A conversion value CH0 (E1) (aoport_dae1_0_data) 1000_7104H D/A conversion value CH1 (E1) (aoport_dae1_1_data) 1000_7106H D/A conversion value CH0 (E2) (aoport_dae2_0_data) 1000_7108H D/A conversion value CH1 (E2) (aoport_dae2_1_data) 1000_710AH...
Page 552: Fpga Register Details (Logging Part)
FPGA register details (logging part) Logging operation control register ■Address Name FPGA register address Logging operation control register (lgdw_ctrl) 1000_9000H ■Description Configure and control the logging operation. The firmware controls. 0 (fixed) 0 (fixed) (fixed) (1) Start logging (7) Automatic transfer mode (logging part) •...
Page 553 Logging state register ■Address Name FPGA register address Logging state register (lgdw_sts) 1000_9002H ■Description The status of the logging part can be checked. 0 (fixed) 0 (fixed) 0 (fixed) (fixed) (1) Start logging (user circuit) • 1: Start logging (write enabled) •...
Page 554 Logging system flag ■Address Name FPGA register address Logging system flag (lgdw_sys_sts) 1000_9004H ■Description The status of the logging system flag can be checked. 0 (fixed) (fixed) (1) Current status of buffer (FIFO) full (6) User sampling pulse cycle error (less than cycle 1s) •...
Page 555 Flag clear register ■Address Name FPGA register address Flag clear register (lgdw_flag_clr) 1000_9006H ■Description Clears the logging state register and logging system flags. All bits of the flag clear register are cleared by writing 1 to the corresponding bit. 0 is always read when reading. 0 (fixed) 0 (fixed) 0 (fixed)
Page 556 Time information ■Address Name FPGA register address Time information (year) (lgdw_clock_rddata1) 1000_9030H Time information (month, day, hour) (Igdw_clock_rddata2) 1000_9032H Time information (minutes, seconds) (lgdw_clock_rddata3) 1000_9034H Time information (ms) (lgdw_clock_rddata4) 1000_9036H Time information (s) (lgdw_clock_rddata5) 1000_9038H ■Description Time information. Read data (data added in the logging part) FPGA register address 1000_9030H...
Page 557 Set number of sampling after trigger ■Address Name FPGA register address Set number of sampling after trigger (lower side) (lgdw_triggered_lsample) 1001_9000H Set number of sampling after trigger (upper side) (lgdw_triggered_usample) 1001_9002H ■Description Sets the number of times logging occurs after trigger input. FPGA register address 1001_9000H...
Page 558 Number of samplings ■Address Name FPGA register address Number of samplings (lower) (lgdw_sample_lcount) 1001_9004H Number of samplings (upper) (lgdw_sample_ucount) 1001_9006H ■Description The number of samplings of logging data can be checked. • It does not count beyond FFFF_FFFFH. • Cleared when logging starts. ■FPGA initial value 0000H ■Firmware initial value...
Page 559: Fpga Register Details (User Circuit)
FPGA register details (user circuit) Write/read data control register ■Address Name FPGA register address Write/read data control register (usr_wrdat_ctrl) 1000_A000H ■Description The firmware controls this register and transfers data to the user circuit. • When 1 is written to write data control (transient area/cyclic area) and read data control (transient area/cyclic area), it is automatically cleared by hardware.
Page 560 User circuit logging mode selection ■Address Name FPGA register address User circuit logging mode selection (usr_logmode_sel) 1000_A002H ■Description Sets the non-time division/time division mode (time division enabled/disabled). • Non-time division mode (time division disabled): Logs 512-bit (1 record) data together with time information for each sampling.
Page 561 MCU system error notification ■Address Name FPGA register address MCU system error notification (usr_micon_syserr) 1000_A004H ■Description This register notifies the system error from the microcomputer to FPGA. Since this is a register for future extension, the setting cannot be changed from No error (0). 0 (fixed) (1) MCU system error notification •...
Page 562 Always write register 0 ■Address Name FPGA register address Always write register 0 (usr_alwreg_00) 1000_A010H ■Description Stores the value to be output to the user circuit when "USER switch enable/disable" is "disable". Stores the states of function setting switches 7 to 10 when "User switch enable/disable" is "enable". 0 (fixed) (1) Function setting switch 10 •...
Page 563 Always write register 13 ■Address Name FPGA register address Always write register 13 (usr_alwreg_0D) 1000_A02AH ■Description Stores the value to be output to the user circuit, and the status for each synchronization cycle of the master station when using the CC-Link IE TSN network synchronous communication function. •...
Page 564 Always write register 15 ■Address Name FPGA register address Always write register 15 (usr_alwreg_0F) 1000_A02EH ■Description The statuses of the logging data FTP transfer and FPGA control processing can be checked. By checking the status of FPGA control processing, it can be used as the timing to start LDAC output. 0 (fixed) (1) Status of FPGA control start processing •...
Page 565 Write data ■Address Name FPGA register address Writing data (transient area) (usr_wreg_000 to usr_wreg_17F) 1000_B000H to 1000_B2FFH Writing data (cyclic area) (usr_wreg_180 to usr_wreg_1FF) 1000_B300H to 1000_B3FFH ■Description Stores the value to be output to the user circuit. ■FPGA initial value 0000H ■Firmware initial value 0000H...
Page 566: Fpga Register Details (Sample Circuit Register)
FPGA register details (sample circuit register) The following functions are implemented to control the circuit to be implemented in the sample circuit. • Always write register • Always read register • Write data • Read Data Write/read data control register ■Address Name FPGA register address...
Page 567 User circuit logging mode selection ■Address Name FPGA register address User circuit logging mode selection (usr_logmode_sel) 1000_A002H ■Description Sets the non-time division/time division mode (time division enabled/disabled). • Non-time division mode (time division disabled): Logs 512-bit (1 record) data together with time information for each sampling.
Page 568 MCU system error notification ■Address Name FPGA register address MCU system error notification (usr_micon_syserr) 1000_A004H ■Description This register notifies the system error from the microcomputer to FPGA. Since this is a register for future extension, the setting cannot be changed from No error (0). 0 (fixed) (1) MCU system error notification •...
Page 569 Always write register areas 1 to 12 ■Address Name FPGA register address Always write register 1 (usr_alwreg_01) to Constant write register 12 (usr_alwreg_0C) 1000_A012H to 1000_A029H ■Description Stores the value to be output to the user circuit. ■FPGA initial value 0000H ■Firmware initial value 0000H...
Page 570 Always write register 13 ■Address Name FPGA register address Always write register 13 (usr_alwreg_0D) 1000_A02AH ■Description Stores the value to be output to the user circuit, and the status for each synchronization cycle of the master station when using the CC-Link IE TSN network synchronous communication function. •...
Page 571 Always write register 15 ■Address Name FPGA register address Always write register 15 (usr_alwreg_0F) 1000_A02EH ■Description The statuses of the logging data FTP transfer and FPGA control processing can be checked. By checking the status of FPGA control processing, it can be used as the timing to start LDAC output. 0 (fixed) (1) Status of FPGA control start processing •...
Page 572 Always read register 0 ■Address Name FPGA register address Always read register 0 (usr_alrreg_00) 1000_A030H ■Description The signal from the user circuit is stored when "USER switch enable/disable" is "disable". Stores the states of function setting switches 7 to 10 when "User switch enable/disable" is "enable". 0 (fixed) (1) Function setting switch 10 •...
Page 573 Always read register 13 ■Address Name FPGA register address Always read register 13 (usr_alwreg_0D) 1000_A04AH ■Description Stores the signal from the user circuit, and the status for each synchronization cycle of the master station when using the CC- Link IE TSN network synchronous communication function. •...
Page 574 Always read register 15 ■Address Name FPGA register address Always read register 15 (usr_alwreg_0F) 1000_A04EH ■Description The statuses of the logging data FTP transfer and FPGA control processing can be checked. By checking the status of FPGA control processing, it can be used as the timing to start LDAC output. 0 (fixed) (1) Status of FPGA control start processing •...
Page 575 Digital control part enable/disable control register ■Address Name FPGA register address Digital control part enable/disable control register (IOB0_X0 B0) (usr_wreg_000) 1000_B000H Digital control part enable/disable control register (IOB0_X1 B0) (usr_wreg_001) 1000_B002H Digital control part enable/disable control register (IOB0_X2 B0) (usr_wreg_002) 1000_B004H Digital control part enable/disable control register (IOB0_X3 B0) (usr_wreg_003) 1000_B006H...
Page 576 Name FPGA register address Digital control part enable/disable control register (IOE0_X1 E0) (usr_wreg_03D) 1000_B07AH Digital control part enable/disable control register (IOE0_X2 E0) (usr_wreg_03E) 1000_B07CH Digital control part enable/disable control register (IOE0_X3 E0) (usr_wreg_03F) 1000_B07EH Digital control part enable/disable control register (IOE0_X4 E0) (usr_wreg_040) 1000_B080H Digital control part enable/disable control register (IOE0_X5 E0) (usr_wreg_041) 1000_B082H...
Page 577 ■Description Sets the digital output signal (after digital control) of the digital control part. When the digital output is enabled, the digital control part outputs the digital input signal (after filtering) from the digital input control part in inversion output or through output. When the digital output is disabled, the digital output signal (after digital control) is fixed to 0.
Page 578 Digital output control digital output selection ■Address Name FPGA register address Digital output control digital output selection (B0) (usr_wreg_078) 1000_B0F0H Digital output control digital output selection (B1) (usr_wreg_079) 1000_B0F2H Digital output control digital output selection (B2) (usr_wreg_07A) 1000_B0F4H Digital output control digital output selection (E0) (usr_wreg_07B) 1000_B0F6H Digital output control digital output selection (E1) (usr_wreg_07C) 1000_B0F8H...
Page 579 Digital I/O control I/O control register ■Address Name FPGA register address Digital I/O control I/O control register (B0) (usr_wreg_080) 1000_B100H Digital I/O control I/O control register (B1) (usr_wreg_081) 1000_B102H Digital I/O control I/O control register (B2) (usr_wreg_082) 1000_B104H Digital I/O control I/O control register (E0) (usr_wreg_083) 1000_B106H Digital I/O control I/O control register (E1) (usr_wreg_084) 1000_B108H...
Page 580 Digital I/O control digital output selection ■Address Name FPGA register address Digital I/O control digital output selection (usr_wreg_086) 1000_B10CH ■Description Selects the signal to be output from the user circuit to the digital I/O control part of the standard circuit. Either the digital control part or the pulse output part can be selected as the output source.
Page 581 Digital output HOLD/CLEAR ■Address Name FPGA register address Digital output HOLD/CLEAR (usr_wreg_088) 1000_B110H ■Description Controls HOLD/CLEAR of digital output. 0 (fixed) (1) HOLD/CLEAR setting • 1: HOLD • 0: CLEAR ■FPGA initial value ■Firmware initial value ■Reset cause Reset Logging control part logging enable signal selection ■Address Name FPGA register address...
Page 582 Logging control part end trigger signal selection ■Address Name FPGA register address Logging control part end trigger signal selection (usr_wreg_092) 1000_B124H ■Description Selects the logging end trigger signal of the logging control part. 0 (fixed) End trigger signal selection • 15H: b1 of the logging •...
Page 583 Logging control part sampling pulse signal selection ■Address Name FPGA register address Logging control part sampling pulse signal selection (usr_wreg_093) 1000_B126H ■Description Selects the user sampling pulse signal of the logging control part. 0 (fixed) Sampling pulse signal selection • 17H: A/D conversion value •...
Page 584 Logging control part logging enable mode setting ■Address Name FPGA register address Logging control part logging enable mode setting (usr_wreg_094) 1000_B128H ■Description Selects the mode of the logging enable signal. 0 (fixed) (1) Logging enable mode setting • 1: 1 enable mode •...
Page 585 Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value ■Address Name FPGA register address Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit (lower side) (B0) (usr_wreg_0A3) 1000_B146H Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit (upper side) (B0) (usr_wreg_0A4) 1000_B148H Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit (lower side) (B1) (usr_wreg_0AB) 1000_B156H...
Page 586 Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection ■Address Name FPGA register address Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B0) (usr_wreg_0A5) 1000_B14AH Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B1) (usr_wreg_0AD) 1000_B15AH Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B2) (usr_wreg_0B5) 1000_B16AH...
Page 587 Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit value ■Address Name FPGA register address Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit value (lower side) (B0) (usr_wreg_0D3) 1000_B1A6H Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit value (upper side) (B0) (usr_wreg_0D4) 1000_B1A8H Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit value (lower side) (B1) (usr_wreg_0DB) 1000_B1B6H...
Page 588 Counter control part 32-bit ring counter (1-phase multiple of 1) input signal selection ■Address Name FPGA register address Counter control part 32-bit ring counter (1-phase multiple of 1) input signal selection (B0) (usr_wreg_0D5) 1000_B1AAH Counter control part 32-bit ring counter (1-phase multiple of 1) input signal selection (B1) (usr_wreg_0DD) 1000_B1BAH Counter control part 32-bit ring counter (1-phase multiple of 1) input signal selection (B2) (usr_wreg_0E5) 1000_B1CAH...
Page 589 Pulse output part pulse width upper limit value ■Address Name FPGA register address Pulse output part pulse width upper limit value (lower side) (B0) (usr_wreg_110) 1000_B220H Pulse output part pulse width upper limit value (upper side) (B0) (usr_wreg_111) 1000_B222H Pulse output part pulse width upper limit value (lower side) (B1) (usr_wreg_115) 1000_B22AH Pulse output part pulse width upper limit value (upper side) (B1) (usr_wreg_116) 1000_B22CH...
Page 590 Pulse output part output pulse count upper limit value ■Address Name FPGA register address Pulse output part output pulse count upper limit value (lower side) (B0) (usr_wreg_112) 1000_B224H Pulse output part output pulse count upper limit value (upper side) (B0) (usr_wreg_113) 1000_B226H Pulse output part output pulse count upper limit value (lower side) (B1) (usr_wreg_117) 1000_B22EH...
Page 591 Pulse output part pulse output selection ■Address Name FPGA register address Pulse output part pulse output selection 0 (B0) (usr_wreg_130) 1000_B260H Pulse output part pulse output selection 1 (B0) (usr_wreg_131) 1000_B262H Pulse output part pulse output selection 2 (B0) (usr_wreg_132) 1000_B264H Pulse output part pulse output selection 0 (B1) (usr_wreg_133) 1000_B266H...
Page 592 Pulse output part pulse output mask ■Address Name FPGA register address Pulse output part pulse output mask 0 (B0) (usr_wreg_142) 1000_B284H Pulse output part pulse output mask 1 (B0) (usr_wreg_143) 1000_B286H Pulse output part pulse output mask 0 (B1) (usr_wreg_144) 1000_B288H Pulse output part pulse output mask 1 (B1) (usr_wreg_145) 1000_B28AH...
Page 593 Analog output part LDAC output selection ■Address Name FPGA register address Analog output part LDAC output selection (usr_wreg_160) 1000_B2C0H ■Description Select LDAC1 or LDAC0 output. 0 (fixed) (1) E0 LDAC1, LDAC0 output • 11: 11b output • 10: LDAC output for inter-channel synchronization •...
Page 594 Test mode setting ■Address Name FPGA register address Test mode setting (usr_wreg_17F) 1000_B2FEH ■Description When the test mode is enabled, the value of write data (cyclic area) is transferred to read data (cyclic area). When the test mode is disabled, the status of the user circuit is transferred to the read data (cyclic area). 0 (fixed) (1) Test mode function enable/disable •...
Page 595 Logging control part 1 enable clear ■Address Name FPGA register address Logging control part 1 enable clear (usr_wreg_181) 1000_B302H ■Description 1 Clears the logging enable signal in enable mode. 0 (fixed) (1) 1 logging enable clear setting • 1: 1 enable mode clear ■FPGA initial value ■Firmware initial value ...
Page 596 Counter control part 32-bit ring counter (2-phase multiple of 4) preset data ■Address Name FPGA register address Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower side) (B0) (usr_wreg_189) 1000_B312H Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (upper side) (B0) (usr_wreg_18A) 1000_B314H Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower side) (B1) (usr_wreg_18C) 1000_B318H...
Page 597 Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction ■Address Name FPGA register address Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction (B0) (usr_wreg_1A0) 1000_B340H Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction (B1) (usr_wreg_1A3) 1000_B346H Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction (B2) (usr_wreg_1A6) 1000_B34CH...
Page 598 Counter control part 32-bit ring counter (1-phase multiple of 1) preset data ■Address Name FPGA register address Counter control part 32-bit ring counter (1-phase multiple of 1) preset data (lower side) (B0) (usr_wreg_1A1) 1000_B342H Counter control part 32-bit ring counter (1-phase multiple of 1) preset data (upper side) (B0) (usr_wreg_1A2) 1000_B344H Counter control part 32-bit ring counter (1-phase multiple of 1) preset data (lower side) (B1) (usr_wreg_1A4) 1000_B348H...
Page 599 Pulse output part pulse output enable ■Address Name FPGA register address Pulse output part pulse output enable (B0) (usr_wreg_1B8) 1000_B370H Pulse output part pulse output enable (B1) (usr_wreg_1B9) 1000_B372H Pulse output part pulse output enable (B2) (usr_wreg_1BA) 1000_B374H Pulse output part pulse output enable (E0) (usr_wreg_1BB) 1000_B376H Pulse output part pulse output enable (E1) (usr_wreg_1BC) 1000_B378H...
Page 600 Analog output part D/A conversion value enable ■Address Name FPGA register address Analog output part D/A conversion value enable (usr_wreg_1C6) 1000_B38CH ■Description Outputs 1 pulse of the data update timing to the analog output control part, and performs the D/A conversion for the analog output part D/A conversion value.
Page 601 Analog control data sampling pulse generation ■Address Name FPGA register address Analog control data sampling pulse generation (usr_wreg_1C8) 1000_B390H ■Description Outputs the data sampling of the analog input control part. 0 (fixed) (1) Analog control data sampling pulse generation (B0) •...
Page 602 User circuit part error signal generation ■Address Name FPGA register address User circuit part error signal generations (usr_wreg_1D0) 1000_B3A0H ■Description Generates an error signal to output from the user circuit. 0 (fixed) (1) User circuit: Error signal generation • 1: (1) Output •...
Page 603 A/D conversion value maximum/minimum current value update ■Address Name FPGA register address A/D conversion value maximum/minimum current value update (usr_wreg_1D9) 1000_B3B2H ■Description Updates the maximum and minimum values of A/D conversion values of E0 to E2 to the current values. 0 (fixed) (1) A/D conversion value maximum/minimum value: Current value update(E0) •...
Page 604 Module type signal (main) ■Address Name FPGA register address Module type signal (main) (usr_rreg_180) 1000_BB00H ■Description The module type of the circuit board connected to the connector (B0 to B2) of the main module is stored. 0 (fixed) (1) Module type (B0) (IOB0_UNIT[3:0]) •...
Page 605 Module type signal (extension) ■Address Name FPGA register address Module type signal (extension) (usr_rreg_181) 1000_BB02H ■Description Stores the module type of the circuit board connected to the connector (E0 to E2) of the extension module. 0 (fixed) (1) Module type (E0 to E2) (IOE_UNIT[4:0]) •...
Page 606 Digital input (after filtering) IOB0_DIO485_I ■Address Name FPGA register address Digital input (after filtering) IOB0_DIO485_I (B0) (usr_rreg_183) 1000_BB06H Digital input (after filtering) IOB0_DIO485_I (B1) (usr_rreg_185) 1000_BB0AH Digital input (after filtering) IOB0_DIO485_I (B2) (usr_rreg_187) 1000_BB0EH Digital input (after filtering) IOB0_DIO485_I (E0) (usr_rreg_189) 1000_BB12H Digital input (after filtering) IOB0_DIO485_I (E1) (usr_rreg_18B) 1000_BB16H...
Page 607 Analog control A/D conversion value ■Address Name FPGA register address Analog control A/D conversion value CH0 (E0) (usr_rreg_18F) 1000_BB1EH Analog control A/D conversion value CH1 (E0) (usr_rreg_190) 1000_BB20H Analog control A/D conversion value CH2 (E0) (usr_rreg_191) 1000_BB22H Analog control A/D conversion value CH3 (E0) (usr_rreg_192) 1000_BB24H Analog control A/D conversion value CH4 (E0) (usr_rreg_193) 1000_BB26H...
Page 608 Counter control part 32-bit ring counter (2-phase multiple of 4) counter value ■Address Name FPGA register address Counter control part 32-bit ring counter (2-phase multiple of 4) counter value (lower side) (B0) (usr_rreg_1B3) 1000_BB66H Counter control part 32-bit ring counter (2-phase multiple of 4) counter value (upper side) (B0) (usr_rreg_1B4) 1000_BB68H Counter control part 32-bit ring counter (2-phase multiple of 4) counter value (lower side) (B1) (usr_rreg_1B5) 1000_BB6AH...
Page 609 Counter control part 32-bit ring counter (1-phase multiple of 1) counter value ■Address Name FPGA register address Counter control part 32-bit ring counter (1-phase multiple of 1) counter value (lower side) (B0) (usr_rreg_1BF) 1000_BB7EH Counter control part 32-bit ring counter (1-phase multiple of 1) counter value (upper side) (B0) (usr_rreg_1C0) 1000_BB80H Counter control part 32-bit ring counter (1-phase multiple of 1) counter value (lower side) (B1) (usr_rreg_1C1) 1000_BB82H...
Page 610 Pulse output part output pulse count ■Address Name FPGA register address Pulse output part output pulse count (lower side) (B0) (usr_rreg_1CB) 1000_BB96H Pulse output part output pulse count (upper side) (B0) (usr_rreg_1CC) 1000_BB98H Pulse output part output pulse count (lower side) (B1) (usr_rreg_1CD) 1000_BB9AH Pulse output part output pulse count (upper side) (B1) (usr_rreg_1CE) 1000_BB9CH...
Page 611 Minimum A/D conversion value ■Address Name FPGA register address Minimum A/D conversion value CH0 (usr_rreg_1E3) 1000_BBC6H Minimum A/D conversion value CH1 (usr_rreg_1E4) 1000_BBC8H Minimum A/D conversion value CH2 (usr_rreg_1E5) 1000_BBCAH Minimum A/D conversion value CH3 (usr_rreg_1E6) 1000_BBCCH Minimum A/D conversion value CH4 (usr_rreg_1E7) 1000_BBCEH Minimum A/D conversion value CH5 (usr_rreg_1E8) 1000_BBD0H...
Page 612: Appendix 5 List Of User Circuit Block Terminals
Appendix 5 List of User Circuit Block Terminals The list of external terminals of the user circuit block is shown below. Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name ...
Page 613 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Analog input u_ai2_top_e0 ai_ioe0_aival_9_cl A/D conversion Input 0000H 100MHz clk100m control part k100m_reg value CH9(E0) Analog input u_ai2_top_e0 ai_ioe0_aival_a_cl A/D conversion Input...
Page 614 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name  Timing u_tg2_top tg_05us_tmgpulse 0.5us sampling Input 100MHz clk100m generator _clk100m_1shot_r pulse for user circuit   FPGA external top1 IOB0_UNIT Module type (B0) Input...
Page 615 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_0 Write data 6 Input 0000H 100MHz clk100m 06_clk100m_reg Register part u_re2_top re_rs_usr_wreg_0 Write data 7 Input ...
Page 616 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_0 Write data 35 Input 0000H 100MHz clk100m 23_clk100m_reg   Register part u_re2_top re_rs_usr_wreg_0 Write data 36 Input 0000H...
Page 617 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_0 Write data 64 Input 0000H 100MHz clk100m 40_clk100m_reg Register part u_re2_top re_rs_usr_wreg_0 Write data 65 Input ...
Page 618 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_0 Write data 93 Input 0000H 100MHz clk100m 5d_clk100m_reg   Register part u_re2_top re_rs_usr_wreg_0 Write data 94 Input 0000H...
Page 619 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_0 Write data 122 Input 0000H 100MHz clk100m 7a_clk100m_reg Register part u_re2_top re_rs_usr_wreg_0 Write data 123 Input ...
Page 620 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_0 Write data 151 Input 0000H 100MHz clk100m 97_clk100m_reg   Register part u_re2_top re_rs_usr_wreg_0 Write data 152 Input 0000H...
Page 621 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_0 Write data 180 Input 0000H 100MHz clk100m b4_clk100m_reg Register part u_re2_top re_rs_usr_wreg_0 Write data 181 Input ...
Page 622 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_0 Write data 209 Input 0000H 100MHz clk100m d1_clk100m_reg   Register part u_re2_top re_rs_usr_wreg_0 Write data 210 Input 0000H...
Page 623 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_0 Write data 238 Input 0000H 100MHz clk100m ee_clk100m_reg Register part u_re2_top re_rs_usr_wreg_0 Write data 239 Input ...
Page 624 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_1 Write data 267 Input 0000H 100MHz clk100m 0b_clk100m_reg   Register part u_re2_top re_rs_usr_wreg_1 Write data 268 Input 0000H...
Page 625 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_1 Write data 296 Input 0000H 100MHz clk100m 28_clk100m_reg Register part u_re2_top re_rs_usr_wreg_1 Write data 297 Input ...
Page 626 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_1 Write data 325 Input 0000H 100MHz clk100m 45_clk100m_reg   Register part u_re2_top re_rs_usr_wreg_1 Write data 326 Input 0000H...
Page 627 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_1 Write data 354 Input 0000H 100MHz clk100m 62_clk100m_reg Register part u_re2_top re_rs_usr_wreg_1 Write data 355 Input ...
Page 628 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_1 Write data 383 Input 0000H 100MHz clk100m 7f_clk100m_reg   Register part u_re2_top re_rs_usr_wreg_1 Write data 384 Input 0000H...
Page 629 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_1 Write data 412 Input 0000H 100MHz clk100m 9c_clk100m_reg Register part u_re2_top re_rs_usr_wreg_1 Write data 413 Input ...
Page 630 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_1 Write data 441 Input 0000H 100MHz clk100m b9_clk100m_reg   Register part u_re2_top re_rs_usr_wreg_1 Write data 442 Input 0000H...
Page 631 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_1 Write data 470 Input 0000H 100MHz clk100m d6_clk100m_reg Register part u_re2_top re_rs_usr_wreg_1 Write data 471 Input ...
Page 632 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_wreg_1f Write data 499 Input 0000H 100MHz clk100m 3_clk100m_reg   Register part u_re2_top re_rs_usr_wreg_1f Write data 500 Input 0000H...
Page 633 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Digital I/O u_dio2_top_e0 uc_ioe0_dio485_o Digital output Output 100MHz clk100m control part _clk100m_reg signal (digital I/O   Digital I/O u_dio2_top_e0 uc_ioe0_dio485_e Digital I/O control...
Page 634 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top uc_rs_usr_alrreg_ Always read Output 0000H 100MHz clk100m 05_clk100m_reg register 5   Register part u_re2_top uc_rs_usr_alrreg_ Always read Output...
Page 635 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_01 Read data 18 Output 0000H 100MHz clk100m 2_clk100m_reg Register part u_re2_top re_rs_usr_rreg_01 Read data 19 Output ...
Page 636 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_02f Read data 47 Output 0000H 100MHz clk100m _clk100m_reg   Register part u_re2_top re_rs_usr_rreg_03 Read data 48 Output 0000H...
Page 637 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_04 Read data 76 Output 0000H 100MHz clk100m c_clk100m_reg Register part u_re2_top re_rs_usr_rreg_04 Read data 77 Output ...
Page 638 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_06 Read data 105 Output 0000H 100MHz clk100m 9_clk100m_reg   Register part u_re2_top re_rs_usr_rreg_06 Read data 106 Output 0000H...
Page 639 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_08 Read data 134 Output 0000H 100MHz clk100m 6_clk100m_reg Register part u_re2_top re_rs_usr_rreg_08 Read data 135 Output ...
Page 640 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_0a Read data 163 Output 0000H 100MHz clk100m 3_clk100m_reg   Register part u_re2_top re_rs_usr_rreg_0a Read data 164 Output 0000H...
Page 641 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_0c Read data 192 Output 0000H 100MHz clk100m 0_clk100m_reg Register part u_re2_top re_rs_usr_rreg_0c Read data 193 Output ...
Page 642 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_0d Read data 221 Output 0000H 100MHz clk100m d_clk100m_reg   Register part u_re2_top re_rs_usr_rreg_0d Read data 222 Output 0000H...
Page 643 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_0fa Read data 250 Output 0000H 100MHz clk100m _clk100m_reg Register part u_re2_top re_rs_usr_rreg_0fb Read data 251 Output ...
Page 644 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_11 Read data 279 Output 0000H 100MHz clk100m 7_clk100m_reg   Register part u_re2_top re_rs_usr_rreg_11 Read data 280 Output 0000H...
Page 645 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_13 Read data 308 Output 0000H 100MHz clk100m 4_clk100m_reg Register part u_re2_top re_rs_usr_rreg_13 Read data 309 Output ...
Page 646 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_15 Read data 337 Output 0000H 100MHz clk100m 1_clk100m_reg   Register part u_re2_top re_rs_usr_rreg_15 Read data 338 Output 0000H...
Page 647 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_16 Read data 366 Output 0000H 100MHz clk100m e_clk100m_reg Register part u_re2_top re_rs_usr_rreg_16f Read data 367 Output ...
Page 648 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_18 Read data 395 Output 0000H 100MHz clk100m b_clk100m_reg   Register part u_re2_top re_rs_usr_rreg_18 Read data 396 Output 0000H...
Page 649 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_1a Read data 424 Output 0000H 100MHz clk100m 8_clk100m_reg Register part u_re2_top re_rs_usr_rreg_1a Read data 425 Output ...
Page 650 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_1c Read data 453 Output 0000H 100MHz clk100m 5_clk100m_reg   Register part u_re2_top re_rs_usr_rreg_1c Read data 454 Output 0000H...
Page 651 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_1e Read data 482 Output 0000H 100MHz clk100m 2_clk100m_reg Register part u_re2_top re_rs_usr_rreg_1e Read data 483 Output ...
Page 652 Connection destination Terminal Input/ Polarity Initial 1shot Sync clock width output value Block name Instance signal Signal name Clock name   Register part u_re2_top re_rs_usr_rreg_1ff Read data 511 Output 0000H 100MHz clk100m _clk100m_reg APPX Appendix 5 List of User Circuit Block Terminals...
Page 653: Appendix 6 A List Of Fpga External Terminals
Appendix 6 A List of FPGA External Terminals A list of FPGA external terminals is shown below. Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency...
Page 654 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 655 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 656 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 657 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 658 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 659 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 660 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 661 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 662 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 663 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 664 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 665 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 666 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 667 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 668 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 669 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 670 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 671 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 672 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 673 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 674 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 675 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 676 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 677 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 678 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 679 Connec- Ter- Exter- Each Func- I/O di- I/O di- Logic Initial state Operating tion cir- minal nal ter- circuit tions rec- rec- type volt- PD in frequency After cuit num- minal board tion tion FPGA set- reset board name func- ting tion ter- each...
Page 680: Appendix 7 I/O Conversion Characteristics And Accuracy
Appendix 7 I/O Conversion Characteristics and Accuracy A/D conversion Voltage input The graph below shows the conversion characteristics during voltage input and the accuracy against the maximum A/D conversion value. Excluded when the wiring is influenced by noise. digit 32767 32439 -32440 -32768...
Page 681 During current input The graph below shows the conversion characteristics during the current input and the accuracy against the maximum A/D conversion value. Excluded when the wiring is influenced by noise. digit 32767 32439 -32440 -32768 -19.8 19.8 digit: A/D conversion value mA: Analog input current (mA) (1) Fluctuation range (2) Practical analog input range The maximum resolution and accuracy during the current input are shown below.
Page 682: D/A Conversion
D/A conversion During voltage output The graph below shows the conversion characteristics during the voltage output and the accuracy against the maximum analog output value. Excluded when the wiring is influenced by noise. -9.9 32768 65207 65535 digit digit: D/A conversion value V: Analog output voltage (V) (1) Fluctuation range (2) Practical analog output range The maximum resolution and accuracy during the voltage output are shown below.
Page 683 During current output The graph below shows the conversion characteristics during the current output and the accuracy against the maximum analog output value. Excluded when the wiring is influenced by noise. 19.8 32768 64880 65535 digit digit: D/A conversion value mA: Analog output current (mA) (1) Fluctuation range (2) Practical analog output range...
Page 684: Appendix 8 Cc-Link Ie Tsn Processing Time
Appendix 8 CC-Link IE TSN Processing Time The processing time of CC-Link IE TSN is the time until the device operation of the master station CPU module is reflected in the FPGA register, or the time until the state of FPGA register is reflected in the device of the master station CPU module. The CC-Link IE TSN processing time is determined by the following processing time.
Page 685: Appendix 9 Logging Data Ftp Transfer Time
Appendix 9 Logging Data FTP Transfer Time The time to transfer logging data to the FTP server depends on the logging parameters. Examples of parameters and transfer times are shown below. Logging setting parameters Transfer time Logging data format Logging data size (number of Number of targets for CSV records) conversion...
Page 686: Appendix 10 Emc And Low Voltage Directives
Appendix 10 EMC and Low Voltage Directives In each country, laws and regulations concerning electromagnetic compatibility (EMC) and electrical safety are enacted. For the products sold in the European countries, compliance with the EU's EMC Directive has been a legal obligation as EMC regulation since 1996, as well as the EU's Low Voltage Directive as electrical safety regulation since 1997.
Page 687 Test item Test details Standard value EN61000-4-5 A lightning surge is applied to the power line and • AC power line, AC I/O power supply, AC I/O Surge immunity signal line. (unshielded): 2kV CM, 1kV DM • DC power line, DC I/O power supply: 0.5kV CM, DM •...
Page 688 Use shielded cables for external wiring and ground the shields of the external wiring cables to the control panel with the AD75CK cable clamp (manufactured by Mitsubishi Electric Corporation). (Ground the shield section 20 to 30cm away from the module.)
Page 689 Others ■Ferrite core Ferrite cores are effective in reducing radiation noise of 30 to 200MHz. It is recommended to attach ferrite cores to the I/O cables coming out of the control panel. For I/O cables, attach the ferrite cores at the position closest to the cable hole inside the control panel. When attaching the ferrite core, pass the cable through a hole of the ferrite core.
Page 690 FPGA circuit Do not change the source code of the standard circuit part provided by Mitsubishi. For each input filter, set a condition that is recommended by Mitsubishi or higher. APPX Appendix 10 EMC and Low Voltage Directives...
Page 691: Requirements For Compliance With The Low Voltage Directive
Requirements for compliance with the Low Voltage Directive The module operates at the rated voltage of 24VDC. The Low Voltage Directive is not applied to the modules that operate at the rated voltage of less than 50VAC and 75VDC. APPX Appendix 10 EMC and Low Voltage Directives...
Page 692: Appendix 11 How To Check Production Information And Firmware Version
Appendix 11 How to Check Production Information and Firmware Version Checking the production information The manufacturing information of the FPGA module can be checked below. • Rating plate • CC-Link IE TSN/CC-Link IE Field Diagnostics Checking on the rating plate ■Main module (1) MAC address (2) Production information...
Page 693: Checking The Firmware Version
Checking by using CC-Link IE TSN/CC-Link IE Field diagnostics Operating procedure Connect the engineering tool to the CPU module. Start CC-Link IE TSN/CC-Link IE Field diagnostics from the menu. [Diagnostics]  [CC-Link IE TSN/CC-Link IE Field Diagnostics] Right-click the device station and then select "Production Information" to display the production information. The production information appears.
Page 694: Appendix 12 Port Number
Appendix 12 Port Number The following table lists the port numbers of FPGA module. System port numbers cannot be specified. Use a port number that matches the content of communication with the communication destination and the communication method. Port Number Application Decimal Hexadecimal...
Page 695: Appendix 13 Warning List
Appendix 13 Warning List Sample circuit warning list No. Target Corresponding part Description file *.fit.rpt Warning (169133): Can't reserve pin RESERVED_AC13 -- pin name is an illegal or unsupported format Warning about the pin Warning (169133): Can't reserve pin RESERVED_AC19 -- pin name is an illegal or unsupported format assignment for DDR3L Warning (169133): Can't reserve pin RESERVED_AD18 -- pin name is an illegal or unsupported format SDRAM.
Page 696 No. Target Corresponding part Description file *.fit.rpt Critical Warning (11887): The following pin RESERVED_T17 was placed in a reserved GND location. This may Warning about the pin cause decreased performance for HMC. Intel recommends the pin location to be grounded assignment for DDR3L Critical Warning (11887): The following pin RESERVED_AD20 was placed in a reserved GND location.
Page 697 No. Target Corresponding part Description file *.fit.rpt Warning (332174): Ignored filter at pt2_top_ni2_top_cpu.sdc(48): Warning for IP of the *pt2_top_ni2_top_cpu:*|pt2_top_ni2_top_cpu_nios2_oci:the_pt2_top_ni2_top_cpu_nios2_oci|pt2_top_ni2_top_ sample circuit. There is cpu_nios2_oci_debug:the_pt2_top_ni2_top_cpu_nios2_oci_debug|monitor_ready could not be matched with a no problem. keeper File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_ni2_top_cpu.sdc Line: 48 Warning (332049): Ignored set_false_path at pt2_top_ni2_top_cpu.sdc(48): Argument <from> is an empty collection File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/pt2_top_ni2_top_cpu.sdc Line: 48 Warning (332174): Ignored filter at pt2_top_ni2_top_cpu.sdc(49): *pt2_top_ni2_top_cpu:*|pt2_top_ni2_top_cpu_nios2_oci:the_pt2_top_ni2_top_cpu_nios2_oci|pt2_top_ni2_top_...
Page 698 No. Target Corresponding part Description file *.map.rpt Warning (10230): Verilog HDL assignment warning at Warning for IP of the altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of sample circuit. There is target (1) File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/ no problem. altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1170 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of target (1) File: C:/FPGA_release/Layout/db/ip/pt2_top/submodules/...
Page 699 No. Target Corresponding part Description file *.map.rpt Warning (113009): Data at line (7) of memory initialization file "nios_ram_init.hex" is too wide to fit in one Warning for IP of the sample circuit. There is memory word. Wrapping data to subsequent addresses. File: C:/FPGA_release/RTL/TOP/PT/mem_init/ nios_ram_init.hex Line: 7 no problem.
Page 700 No. Target Corresponding part Description file *.map.rpt Warning (14320): Synthesized away node Warning for IP of the "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|sc sample circuit. There is fifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram|q_b[35]" File: C:/FPGA_release/ no problem. Layout/db/altsyncram_3hn1.tdf Line: 1160 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|sc fifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram|q_b[36]" File: C:/FPGA_release/ Layout/db/altsyncram_3hn1.tdf Line: 1192 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|sc fifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram|q_b[37]"...
Page 701 No. Target Corresponding part Description file *.map.rpt Warning (14320): Synthesized away node Warning for IP of the sample circuit. There is "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scf ifo_r871:auto_generated|a_dpfifo_e071:dpfifo|altsyncram_1hn1:FIFOram|q_b[40]" File: C:/FPGA_release/ no problem. Layout/db/altsyncram_1hn1.tdf Line: 1320 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scf ifo_r871:auto_generated|a_dpfifo_e071:dpfifo|altsyncram_1hn1:FIFOram|q_b[41]" File: C:/FPGA_release/ Layout/db/altsyncram_1hn1.tdf Line: 1352 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scf ifo_r871:auto_generated|a_dpfifo_e071:dpfifo|altsyncram_1hn1:FIFOram|q_b[42]"...
Page 702 No. Target Corresponding part Description file *.map.rpt Warning (14320): Synthesized away node Warning for IP of the "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor sample circuit. There is _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener no problem. ated|q_b[5]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 204 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener ated|q_b[6]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 237 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener...
Page 703 No. Target Corresponding part Description file *.map.rpt Warning (14320): Synthesized away node Warning for IP of the sample circuit. There is "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener no problem. ated|q_b[22]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 765 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener ated|q_b[23]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 798 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener...
Page 704 No. Target Corresponding part Description file *.map.rpt Warning (14320): Synthesized away node Warning for IP of the "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor sample circuit. There is _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener no problem. ated|q_b[82]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 2745 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener ated|q_b[83]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 2778 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener...
Page 705 No. Target Corresponding part Description file *.map.rpt Warning (14320): Synthesized away node Warning for IP of the sample circuit. There is "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener no problem. ated|q_b[99]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 3306 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener ated|q_b[100]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 3339 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener...
Page 706 No. Target Corresponding part Description file *.map.rpt Warning (14320): Synthesized away node Warning for IP of the "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor sample circuit. There is _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener no problem. ated|q_b[119]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 3966 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener ated|q_b[120]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 3999 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener...
Page 707 No. Target Corresponding part Description file *.map.rpt Warning (14320): Synthesized away node Warning for IP of the sample circuit. There is "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener no problem. ated|q_b[40]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 1359 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener ated|q_b[41]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 1392 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener...
Page 708 No. Target Corresponding part Description file *.map.rpt Warning (14320): Synthesized away node Warning for IP of the "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor sample circuit. There is _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener no problem. ated|q_b[57]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 1920 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener ated|q_b[58]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 1953 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener...
Page 709 No. Target Corresponding part Description file *.map.rpt Warning (14320): Synthesized away node Warning for IP of the sample circuit. There is "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener no problem. ated|q_b[85]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 2844 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener ated|q_b[86]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 2877 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener...
Page 710 No. Target Corresponding part Description file *.map.rpt Warning (14320): Synthesized away node Warning for IP of the "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor sample circuit. There is _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener no problem. ated|q_b[111]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 3702 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener ated|q_b[121]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 4032 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener...
Page 711 No. Target Corresponding part Description file *.map.rpt Warning (14320): Synthesized away node Warning for IP of the sample circuit. There is "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener no problem. ated|q_b[102]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 3405 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener ated|q_b[103]" File: C:/FPGA_release/Layout/db/altsyncram_p2j1.tdf Line: 3438 Warning (14320): Synthesized away node "pt2_top:u_pt2_top|pt2_top_dm3_top:dm3_top|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor _buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p2j1:auto_gener...
Page 712 No. Target Corresponding part Description file *.map.rpt Warning (10036): Verilog HDL or VHDL warning at is3_inout_sel.v(793): object Signals for future "is_iob0_a_on_d1_clk100m_reg" assigned a value but never read File: C:/FPGA_release/RTL/TOP/IS/ extension are mounted. is3_inout_sel.v Line: 793 It is open on purpose, Warning (10036): Verilog HDL or VHDL warning at is3_inout_sel.v(796): object so there is no problem.
Page 713 No. Name Ignored Entity Ignored Ignored To Ignored Ignored From Value Source Global Signal top1  u_pt2_top|dc3_top|p0|umemphy|uread_dat QSF Assignment apath|reset_n_fifo_wraddress[1]  Global Signal top1 u_pt2_top|dc3_top|p0|umemphy|uread_dat QSF Assignment apath|reset_n_fifo_write_side[0]  Global Signal top1 u_pt2_top|dc3_top|p0|umemphy|uread_dat QSF Assignment apath|reset_n_fifo_write_side[1]  Global Signal top1 u_pt2_top|dc3_top|p0|umemphy|ureset|ph QSF Assignment y_reset_mem_stable_n...
Page 714 Provided pattern warning list No. Target file Corresponding part Description Common to all provided # Warning: DONT_CARE value for read_during_write_mode_port_a is not supported in Stratix It states that Stratix patterns device family, it might cause incorrect behavioural simulation result devices are not supported.
Page 715 No. Name Ignored Entity Ignored Ignored To Ignored Ignored From Value Source Global Signal top1  u_pt2_top|dc3_top|s0|sequencer_rw_mgr_ QSF Assignment inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft _reset_n  D6 Delay (output top1 DDR_DQS_N[0] QSF Assignment register to io buffer) D6 Delay (output top1  DDR_DQS_N[1] QSF Assignment register to io buffer) ...
Page 716: Appendix 14 Logging Data Bit Assignment
Appendix 14 Logging Data Bit Assignment The table below shows the summary of logging target signals. When the user circuit logging mode is the time division mode, 1024-bit signals are logged. No.0 to No.431 are output from the user circuit part block for the first time, and No.432 to No.511 are assigned by the logging control part.
Page 717 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode Digital input signal ch0 (B2 after filtering) Digital input signal ch0 (B2 after filtering) Digital input signal ch1 (B2 after filtering) Digital input signal ch1 (B2 after filtering) Digital input signal ch2 (B2 after filtering)
Page 718 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode Digital input signal ch0 (E2 after filtering) Digital input signal ch0 (E2 after filtering) Digital input signal ch1 (E2 after filtering) Digital input signal ch1 (E2 after filtering) Digital input signal ch2 (E2 after filtering)
Page 719 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode 32-bit ring counter (2-phase multiple of 4) bit[0] 32-bit ring counter (2-phase multiple of 4) (B0) bit[0] (B0) 32-bit ring counter (2-phase multiple of 4) bit[1]...
Page 720 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode 32-bit ring counter (2-phase multiple of 4) 32-bit ring counter (2-phase multiple of 4) bit[16] (B0) bit[16] (B0) 32-bit ring counter (2-phase multiple of 4)
Page 721 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode 32-bit ring counter (2-phase multiple of 4) bit[0] A/D conversion value ch0[0] (E0) (B1) 32-bit ring counter (2-phase multiple of 4) bit[1] A/D conversion value ch0[1] (E0)
Page 722 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode 32-bit ring counter (2-phase multiple of 4) A/D conversion value ch1[0] (E0) bit[16] (B1) 32-bit ring counter (2-phase multiple of 4) A/D conversion value ch1[1] (E0)
Page 723 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode 32-bit ring counter (2-phase multiple of 4) bit[0] A/D conversion value ch3[0] (E0) (B2) 32-bit ring counter (2-phase multiple of 4) bit[1] A/D conversion value ch3[1] (E0)
Page 724 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode 32-bit ring counter (2-phase multiple of 4) A/D conversion value ch4[0] (E0) bit[16] (B2) 32-bit ring counter (2-phase multiple of 4) A/D conversion value ch4[1] (E0)
Page 725 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode 32-bit ring counter (2-phase multiple of 4) bit[0] A/D conversion value ch6[0] (E0) (E0) 32-bit ring counter (2-phase multiple of 4) bit[1] A/D conversion value ch6[1] (E0)
Page 726 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode 32-bit ring counter (2-phase multiple of 4) A/D conversion value ch7[0] (E0) bit[16] (E0) 32-bit ring counter (2-phase multiple of 4) A/D conversion value ch7[1] (E0)
Page 727 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode 32-bit ring counter (2-phase multiple of 4) bit[0] A/D conversion value ch9[0] (E0) (E1) 32-bit ring counter (2-phase multiple of 4) bit[1] A/D conversion value ch9[1] (E0)
Page 728 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode 32-bit ring counter (2-phase multiple of 4) A/D conversion value chA[0] (E0) bit[16] (E1) 32-bit ring counter (2-phase multiple of 4) A/D conversion value chA[1] (E0)
Page 729 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  32-bit ring counter (2-phase multiple of 4) bit[0] (E2) 32-bit ring counter (2-phase multiple of 4) bit[1] ...
Page 730 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  32-bit ring counter (2-phase multiple of 4) bit[16] (E2) ...
Page 731 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode           ...
Page 732 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  Time information [0] (ms) Time information [0] (ms)  Time information [1] (ms) Time information [1] (ms) ...
Page 733 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  Time information [0] (year) Time information [0] (year)  Time information [1] (year) Time information [1] (year) ...
Page 734 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  A/D conversion value ch2[0] (E1)  A/D conversion value ch2[1] (E1) ...
Page 735 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  A/D conversion value ch5[0] (E1)  A/D conversion value ch5[1] (E1) ...
Page 736 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  A/D conversion value ch8[0] (E1)  A/D conversion value ch8[1] (E1) ...
Page 737 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  A/D conversion value chB[0] (E1)  A/D conversion value chB[1] (E1) ...
Page 738 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  A/D conversion value ch2[0] (E2)  A/D conversion value ch2[1] (E2) ...
Page 739 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  A/D conversion value ch5[0] (E2)  A/D conversion value ch5[1] (E2) ...
Page 740 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  A/D conversion value ch8[0] (E2)  A/D conversion value ch8[1] (E2) ...
Page 741 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  A/D conversion value chB[0] (E2)  A/D conversion value chB[1] (E2) ...
Page 742 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode           ...
Page 743 Word Target bit of logging data Logging target list offset (uc_logdat_clk100m_reg) User circuit logging mode is the non- User circuit logging mode is the time division mode time division mode  Time information [0] (seconds) Time information [0] (seconds)  Time information [1] (seconds) Time information [1] (seconds) ...
Page 744: Appendix 15 Open Source Software License
Appendix 15 Open Source Software License Indicates the license of the open source software used in the FPGA Module Configuration Tool. DockPanel Suite (DockPanel Suite Theme2019) ■Overview Library for docking window Themes for docking window (colors and styles) ■Developer (license) GitHub: Weifen Luo (MIT license) ■License terms The MIT License...
Page 745 Nlog ■Overview Logging library ■Developer (license) NLog Project (BSD 3-Clause license) ■License terms Copyright (c) 2004-2021 Jaroslaw Kowalski <jaak@jkowalski.net>, Kim Christensen, Julian Verdurmen All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Page 746 IP address control ■Overview MFC IP input-like IP address input control ■Developer (license) Michael Chapman (MIT license) ■License terms IPAddressControlLib (https://github.com/m66n/ipaddresscontrollib) Copyright (c) 2016 Michael Chapman The MIT License (MIT) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:The above copyright notice and this permission notice shall be included...
Page 747: Appendix 16 Support
For the technical support assistance service regarding the FPGA module, refer to the following table. If you are not sure which type the inquiry belongs to, please consult your local Mitsubishi Electric sales office or representative. Please note that Mitsubishi Electric may not be able to answer to inquiries related to FPGA development software.
Page 748: Appendix 17 External Dimensions
Appendix 17 External Dimensions The figure below shows the external dimensions of the FPGA module. Main module 10.5 (1) DIN rail center (Unit: mm) Extension module 15.5 10.5 (1) DIN rail center (Unit: mm) APPX Appendix 17 External Dimensions...
Page 749 MEMO APPX Appendix 17 External Dimensions...
Page 750: Index
INDEX ....482 Error clear request flag ......476 Error flag External input signal X0 to XF (B0 to B2, E0 to E2) .
Page 751 MEMO...
Page 752: Revisions
Japanese manual number: SH-082568-B This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the contents noted in this manual.
Page 753: Warranty
WARRANTY Please confirm the following product warranty details before using this product. 1. Gratis Warranty Term and Gratis Warranty Range If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the product within the gratis warranty term, the product shall be repaired at no cost via the sales representative or Mitsubishi Service Company.
Page 754: Trademarks
TRADEMARKS Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. QR Code is either a registered trademark or a trademark of DENSO WAVE INCORPORATED in the United States, Japan, and/or other countries. Intel is either a registered trademark or a trademark of Intel Corporation in the United States and/or other countries.
Page 756 SH(NA)-082569ENG-A(2310)MEE MODEL: CCIETSN-FPGA-U-E MODEL CODE: 13JX7E HEAD OFFICE: TOKYO BLDG., 2-7-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN NAGOYA WORKS: 1-14, YADA-MINAMI 5-CHOME, HIGASHI-KU, NAGOYA 461-8670, JAPAN When exported from Japan, this manual does not require application to the Ministry of Economy, Trade and Industry for service transaction permission. Specifications subject to change without notice.

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Nz2gn2s-d41d01 Nz2gn2s-d41pd02 Nz2ex2s-d41p01 Nz2ex2s-d41d01 Nz2ex2s-d41a01

Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Chapter 1 What this Module Can Do

Chapter 2 Product Lineup

Chapter 3 System Configuration

Chapter 4 Part Names

Chapter 5 Specifications

Chapter 6 Procedures before Operation

Chapter 7 Installation and Wiring

Chapter 8 Fpga Module Configuration Tool

Chapter 9 Parameter Setting

Chapter 10 Fpga Development

Chapter 11 Fpga Internal Circuit

Chapter 12 Functions

Chapter 13 Sample Circuit in Standalone Mode

Chapter 14 Sample Circuit in CC-Link Ie Tsn Communication Mode

Chapter 15 Maintenance and Inspection

CHAPTER 16 CC-Link IE TSN/CC-Link IE Field DIAGNOSTICS

Chapter 17 Module Diagnostics with the Fpga Module Configuration Tool

Chapter 18 Checking the Leds

Chapter 19 Unit Test

Chapter 20 Troubleshooting by Symptom

Chapter 21 Troubleshooting During Fpga Development

CHAPTER 22 TROUBLE EXAMPLES of DC INPUT/OUTPUT

Chapter 23 Check/Clear Error Codes

Chapter 24 Error Code List

Appendix 1 Remote I/O Signal

Appendix 2 Remote Register

Appendix 3 Remote Buffer Memory

Appendix 4 FPGA Register

Appendix 5 List of User Circuit Block Terminals

Appendix 6 a List of FPGA External Terminals

Appendix 7 I/O Conversion Characteristics and Accuracy

Appendix 8 CC-Link IE TSN Processing Time

Appendix 9 Logging Data FTP Transfer Time

Appendix 10 EMC and Low Voltage Directives

Appendix 11 How to Check Production Information and Firmware Version

Appendix 12 Port Number

Appendix 13 Warning List

Appendix 14 Logging Data Bit Assignment

Appendix 15 Open Source Software License

Appendix 16 Support

Appendix 17 External Dimensions

Quick Links

Troubleshooting

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Summary of Contents for Mitsubishi Electric NZ2GN2S-D41P01