Nz2Gn2S-D41P01, Nz2Gn2S-D41Pd02, Nz2Ex2S-D41P01 - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

NZ2GN2S-D41P01, NZ2GN2S-D41PD02, NZ2EX2S-D41P01

DC input/output circuit board (input)
The user circuit block timing chart when using the DC input/output circuit board is shown below. In addition, the setting values
of the digital input control part in this timing chart are shown below.
No. Target register
1 Filter sampling pulse (B0)
2 Data sampling timing (B0)
3 Input filter counter upper limit (IOB0_X0) (B0) to input filter counter upper limit (IOB0_XF) (B0)
■Timing chart example
clk100m
Internal operation start/stop [0]
[Digital input control part]
Data sampling pulse
tg_sampling_tmgpulse_0_clk100m_1shot_reg
IOB0_XOEL0
(External terminal output)
IOB0_XOEL1 (External terminal output)
IOB0_X[7:0]
(External terminal input)
Lower side digital input signal fetch
Upper side digital input signal fetch
After lower side digital input signal fetch
After upper side digital input signal fetch
Lower side filter processing
Upper side filter processing
[User circuit block]
Digital input signal (B0 after filtering)
di_iob0_x_clk100m_reg[7:0]
Digital input signal (B0 after filtering)
di_iob0_x_clk100m_reg[15:8]
(1) Filter sampling pulse (B0) = FH, so digital filtering is performed in synchronization with the data sampling timing.
No. Description
1 Sets the internal operation start/stop (mode_ctrl2) (FPGA register address: 1000_0002H) to Start(1).
2 The data sampling timing becomes Enable (1) at each cycle set in "Data sampling timing (B0)", and the digital input control part operates.
3 DC input [7:0] and DC input [15:8] are input from outside the FPGA in time division.
4 A digital input signal that has passed through a digital filter is input to the user circuit block.
*1 B0 is explained at the circuit board. B1, B2, E0, E1, and E2 have the same structure.
*2 Changing the filter sampling pulse (B0) and data sampling timing (B0) changes the input timing of the digital input signal (B0 after
filtering) (di_iob0_x_clk100m_reg[15:0]). For details, refer to the following.
Page 193 Timing generator (tg2_top)
Page 195 Connection and setting value notification timing
(I)
(I) L
(I) L
H
H
14.0ns(max)
(Internal)
L
(Internal) L
(Internal)
(Internal)
(Internal)
(Internal)
(I)
(I)
Setting value
FH
9H
2H each
0.1μs
DC input (lower) DC input (upper) DC input (lower) DC input (upper) DC input (lower)
DC input ([lower])
DC input ([upper]) DC input ([upper])
(1)
Remarks
Data sampling pulse
0.1s cycle

DC input ([upper])
DC input ([lower])
Digital filter processing
Digital filter processing
Digital input (after filtering)
Digital input (after filtering)
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
11
225