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Analog output control part (ao2_top)
If E0 to E2 are analog input/output circuit boards, it controls the DAC (two elements on one circuit board). Communication with
the DAC uses SPI (Serial Peripheral Interface).
In addition, the serial clock output, serial data output signal, and chip select signal are common, and an address (2 bits) for
each chip is used to control the DAC individually.
Synchronization between channels can be performed by controlling the /LDAC signal with the user circuit block.
Top part
(top1)
Register part
DAC setting data
(re2_top)
DAC register address setting
D/A conversion value selection
D/A conversion value CH0/1
D/A conversion value setting timing selection
DAC LDAC signal selection
Timing
Data update timing
generator
(tg2_top)
D/A conversion value (E0)
uc_ioe0_andat_clk100m_reg
User circuit
D/A conversion value enable (E0)
(uc2_top)
uc_ioe0_andat_en_clk100m_reg
LDAC output (E0)
uc_ioe0_ldac_clk100m_reg
*1 This is an analog input/output circuit board. It is described in IOE0. IOE1 and IOE2 have the same structure.
■Function List
Item
Operation
D/A conversion enable/
Enable/disable D/A conversion for each channel.
disable
DAC setting
■DAC setting circuit
Set the DAC (set the register inside the DAC).
■D/A conversion cycle
D/A conversion
processing
The D/A conversion cycle timing pulse can be selected from
"User circuit output" or "Data update timing" by "Select D/A
conversion timing".
■D/A conversion value
D/A conversion value can be selected from "User circuit output"
or "Register setting value" by "Select D/A conversion value".
(The D/A conversion value is output in offset binary.)
■LDAC signal selection
Control of the /LDAC signal by the user circuit block can be
enabled or disabled (fixed to low).
Analog output control part
(ao2_top)
Parallel-to-SPI conversion
DAC data
write
[0]
D/A
conversion
0
value
1
D/A
conversion
0
value enable
1
00b
0
DA_LDACL[1:0]
[1]
1
*1
I/O selector
(is2_top)
IOE0_Y2
IOE0_Y4
IOE0_Y3
IOE0_Y5
open
IOE0_Y6
+3.3V
N.C.
N.C.
IOE0_Y7
+3.3V
N.C.
N.C.
Remarks
F/W controls the DAC setting circuit during the FPGA control
start processing.
D/A conversion processing is performed when "D/A conversion
enable/disable setting" is enabled.
The D/A conversion cycle is set by "Data update timing".
11 FPGA INTERNAL CIRCUIT
DAC0
Spring
CH0
Voltage output
SCLK
clamp
/SYNC
CH0
Current output
terminal
SDI
block
SDO
/LDAC
CLKOUT
/FAULT
AD0
AD1
DAC1
CH1
Voltage output
SCLK
CH1
Current output
/SYNC
SDI
SDO
/LDAC
CLKOUT
/FAULT
AD0
AD1
211
11.3 Standard Circuit
11
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Troubleshooting
