Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 186

User circuit block (sample circuit)
The structure of the factory default user circuit block (sample circuit) is shown below.
Digital signal
Digital input
[15:0]
control part 0
(di2_top)
·
Digital signal
Digital input
[15:0]
control part 5
(di2_top)
Digital signal
Digital I/O
control part 0
(dio2_top)
·
Digital signal
Digital I/O
control part 5
(dio2_top)
Analog input
Analog signal
control part 0
(16bit×12ch)
(ai2_top)
·
Analog signal
Analog input
(16bit×12ch)
control part 2
(ai2_top)
Sampling pulse
Timing
generator
(tg2_top)
Writing data
Register part
Constant write
(re2_top)
data
No. Function blocks
(1) Digital control part
(2) Logging control part
(3) Counter control part
(4) Pulse output part
(5) Analog output part
(6) Pulse generator
(7) Other connections
11 FPGA INTERNAL CIRCUIT
184
11.1 Overview
User circuit block (uc2_top)
(1)
Digital signal
[15:0] [101:0] Digital [101:0]
control part
[95:80]
[96]
[101]
(4)
Pulse signal
[101:0]
Pulse
output part
Counter value (32 bits ×
6ch), phase A and phase
(3)
B inputs (2 bits × 6ch)
Counter [203:0]
control part
(6)
Pulse 1μs pulse output
generator
Internal block
Internal block, 0-fixed output
Function
Inverts digital signals input from the digital input control part and digital input/
output control part, and enables/disables output.
Selects and outputs data to be logged and the signal that controls the logging
part. The logging control part implements the following functions.
• Logging data selection
• Logging enable selection
• Logging end trigger selection
• User sampling pulse selection
Implements the following counters that operate with the signal from the digital
input control part.
• 32-bit ring counter (2-phase multiple of 4)
• 32-bit ring counter (1-phase multiple of 1)
Outputs the following pulses to the digital output control part/digital input/
output control part.
• 0 degree pulse
• 90 degree pulse
• 180 degree pulse
• 270 degree pulse
The pulse can be set in units of 10ns.
Generates the following DAC signals to be connected to the FPGA by register
settings.
• D/A conversion value
• D/A conversion value enable
• LDAC
Generates 1s pulse for logging data generation.
The following functions are implemented as other connections.
• Executes HOLD/CLEAR of digital signals.
• Outputs a user interrupt.
• Controls connection of various signals.
[15:0]
[15:0]
[95:80]
[95:80]
[96]
[96]
[101]
[101]
Logging data
[779:0]
Logging enable
Logging trigger
User sampling pulse
[395:204]
[779:588]
Digital signal[15:0]
Digital signal[15:0]
Digital signal
Digital signal
(2)
Logging data[431:0]
Logging
Logging enable
control
part
Logging end trigger
User sampling pulse
(5)
Analog output data [31:0]
[31:0]
Analog
[0] Analog output enable
output
[1:0] LDAC output [1:0]
part
[63:32] Analog output data [31:0]
[1] Analog output enable
[3:2] LDAC output [1:0]
Analog output data [31:0]
[95:64]
[2] Analog output enable
[5:4] LDAC output [1:0]
Read data
Constant read data
Reference
Page 246 Digital control part (uc3_dig_top)
Page 271 Logging control part (uc3_log_top)
Page 256 Counter control part (uc3_cnt_top)
Page 249 Pulse output part (uc3_plsout)
Page 266 Analog output block (uc3_ao_top)
Page 265 Pulse generator (uc3_pls_top)

Digital output
control part 0
(do2_top)
·
Digital output
control part 5
(do2_top)
Digital I/O
control part 0
(dio2_top)
·
Digital I/O
control part 5
(dio2_top)
Logging part
(lf2_top)
Analog output
control part 0
(ao2_top)
Analog output
control part 1
(ao2_top)
Analog output
control part 2
(ao2_top)
Register part
(re2_top)