Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 622

Connection destination
Block name Instance
name
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
APPX
620
Appendix 5 List of User Circuit Block Terminals
Terminal
signal Signal name
re_rs_usr_wreg_0 Write data 209
d1_clk100m_reg
re_rs_usr_wreg_0 Write data 210
d2_clk100m_reg
re_rs_usr_wreg_0 Write data 211
d3_clk100m_reg
re_rs_usr_wreg_0 Write data 212
d4_clk100m_reg
re_rs_usr_wreg_0 Write data 213
d5_clk100m_reg
re_rs_usr_wreg_0 Write data 214
d6_clk100m_reg
re_rs_usr_wreg_0 Write data 215
d7_clk100m_reg
re_rs_usr_wreg_0 Write data 216
d8_clk100m_reg
re_rs_usr_wreg_0 Write data 217
d9_clk100m_reg
re_rs_usr_wreg_0 Write data 218
da_clk100m_reg
re_rs_usr_wreg_0 Write data 219
db_clk100m_reg
re_rs_usr_wreg_0 Write data 220
dc_clk100m_reg
re_rs_usr_wreg_0 Write data 221
dd_clk100m_reg
re_rs_usr_wreg_0 Write data 222
de_clk100m_reg
re_rs_usr_wreg_0 Write data 223
df_clk100m_reg
re_rs_usr_wreg_0 Write data 224
e0_clk100m_reg
re_rs_usr_wreg_0 Write data 225
e1_clk100m_reg
re_rs_usr_wreg_0 Write data 226
e2_clk100m_reg
re_rs_usr_wreg_0 Write data 227
e3_clk100m_reg
re_rs_usr_wreg_0 Write data 228
e4_clk100m_reg
re_rs_usr_wreg_0 Write data 229
e5_clk100m_reg
re_rs_usr_wreg_0 Write data 230
e6_clk100m_reg
re_rs_usr_wreg_0 Write data 231
e7_clk100m_reg
re_rs_usr_wreg_0 Write data 232
e8_clk100m_reg
re_rs_usr_wreg_0 Write data 233
e9_clk100m_reg
re_rs_usr_wreg_0 Write data 234
ea_clk100m_reg
re_rs_usr_wreg_0 Write data 235
eb_clk100m_reg
re_rs_usr_wreg_0 Write data 236
ec_clk100m_reg
re_rs_usr_wreg_0 Write data 237
ed_clk100m_reg
Bit Input/ Polarity
width output

16 Input

16 Input

16 Input
16 Input 

16 Input

16 Input
16 Input 

16 Input

16 Input

16 Input

16 Input

16 Input
16 Input 

16 Input

16 Input

16 Input
16 Input 

16 Input

16 Input
16 Input 

16 Input

16 Input

16 Input

16 Input

16 Input
16 Input 

16 Input

16 Input

16 Input
Initial 1shot Sync clock
value
Feq

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m