Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 238

Operation when pulse interval constraint is violated
■For user circuit data sampling pulse
User circuit data sampling pulse
Analog input control part
(1) The user circuit data sampling pulse is ignored because A/D conversion processing is in progress.
■For user circuit D/A conversion value enable
User circuit D/A conversion
value enable (E0)
Analog output control part
(1) User circuit D/A conversion value enable (E0) is ignored because D/A conversion processing is in progress.
■For user sampling pulse
User sampling pulse
Logging part
(1) Ignores user sampling pulses because logging is in progress.
Operation when LDAC constraint is violated
■If the width from D/A conversion value enable(1) to LDAC output enable(0) is less than 5.7s
D/A conversion value enable (E0)
uc_ioe0_andat_en_clk100m_reg
IOE0_Y4
(IOE0_DA_SYNCL)
D/A conversion
processing
DAC circuit
processing
D/A conversion
value output
IOE0_Y6/7
(IOE0_DA_LDACL[0]/[1])
(1) Since the D/A conversion processing of the DAC circuit has not been completed, the previous data (D/A conversion processing CH1(1)) may be output.
■If the LDAC output effective period is less than 300ns
D/A conversion value enable (E0)
uc_ioe0_andat_en_clk100m_reg
IOE0_Y4
(IOE0_DA_SYNCL)
D/A conversion
processing
DAC circuit
processing
D/A conversion
value output
IOE0_Y6/7
(IOE0_DA_LDACL[0]/[1])
(1) The D/A conversion processing value may not be output because the DAC circuit does not recognize the LDAC signal.
11 FPGA INTERNAL CIRCUIT
236
11.4 User Circuit Block
4μs or less
A/D conversion processing
6μs or less
D/A conversion processing
(1)
1μs or less
Logging processing
(1)
D/A conversion processing D/A conversion processing D/A conversion processing D/A conversion processing
CH0 CH0 CH1 CH1
(1) (1) (1) (1)
D/A conversion processing CH0 D/A conversion processing CH1
A/D conversion processing
(1)
D/A conversion processing
Logging processing
Less than 5.7μs
D/A conversion processing D/A conversion processing
CH0 CH0
(2) (2)
(1)
Less than 300ns
D/A conversion processing D/A conversion processing
CH1 CH1
(2) (2)
D/A conversion processing D/A conversion processing
value CH0 value CH0
D/A conversion processing D/A conversion processing
value CH1 value CH1
(1)
D/A conversion processing value CH0
D/A conversion processing value CH1
(2) (2)
(1) (1)